fsl,imx35-pinctrl.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller
  8
  9maintainers:
 10  - Dong Aisheng <aisheng.dong@nxp.com>
 11
 12description:
 13  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
 14  for common binding part and usage.
 15
 16allOf:
 17  - $ref: pinctrl.yaml#
 18
 19properties:
 20  compatible:
 21    oneOf:
 22      - enum:
 23          - fsl,imx35-iomuxc
 24          - fsl,imx51-iomuxc
 25          - fsl,imx53-iomuxc
 26          - fsl,imx6dl-iomuxc
 27          - fsl,imx6q-iomuxc
 28          - fsl,imx6sl-iomuxc
 29          - fsl,imx6sll-iomuxc
 30          - fsl,imx6sx-iomuxc
 31          - fsl,imx6ul-iomuxc
 32          - fsl,imx6ull-iomuxc-snvs
 33      - items:
 34          - const: fsl,imx50-iomuxc
 35          - const: fsl,imx53-iomuxc
 36
 37  reg:
 38    maxItems: 1
 39
 40# Client device subnode's properties
 41patternProperties:
 42  'grp$':
 43    type: object
 44    description:
 45      Pinctrl node's client devices use subnodes for desired pin configuration.
 46      Client device subnodes use below standard properties.
 47
 48    properties:
 49      fsl,pins:
 50        description:
 51          each entry consists of 6 integers and represents the mux and config
 52          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
 53          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
 54          be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer
 55          CONFIG is the pad setting value like pull-up on this pin. Please
 56          refer to matching i.MX Reference Manual for detailed CONFIG settings.
 57        $ref: /schemas/types.yaml#/definitions/uint32-matrix
 58        items:
 59          items:
 60            - description: |
 61                "mux_reg" indicates the offset of mux register.
 62            - description: |
 63                "conf_reg" indicates the offset of pad configuration register.
 64            - description: |
 65                "input_reg" indicates the offset of select input register.
 66            - description: |
 67                "mux_val" indicates the mux value to be applied.
 68            - description: |
 69                "input_val" indicates the select input value to be applied.
 70            - description: |
 71                "pad_setting" indicates the pad configuration value to be applied.
 72                Common i.MX35
 73                  PAD_CTL_DRIVE_VOLAGAGE_18       (1 << 13)
 74                  PAD_CTL_DRIVE_VOLAGAGE_33       (0 << 13)
 75                  PAD_CTL_HYS                     (1 << 8)
 76                  PAD_CTL_PKE                     (1 << 7)
 77                  PAD_CTL_PUE                     (1 << 6)
 78                  PAD_CTL_PUS_100K_DOWN           (0 << 4)
 79                  PAD_CTL_PUS_47K_UP              (1 << 4)
 80                  PAD_CTL_PUS_100K_UP             (2 << 4)
 81                  PAD_CTL_PUS_22K_UP              (3 << 4)
 82                  PAD_CTL_ODE_CMOS                (0 << 3)
 83                  PAD_CTL_ODE_OPENDRAIN           (1 << 3)
 84                  PAD_CTL_DSE_NOMINAL             (0 << 1)
 85                  PAD_CTL_DSE_HIGH                (1 << 1)
 86                  PAD_CTL_DSE_MAX                 (2 << 1)
 87                  PAD_CTL_SRE_FAST                (1 << 0)
 88                  PAD_CTL_SRE_SLOW                (0 << 0)
 89                Common i.MX50/i.MX51/i.MX53 bits
 90                  PAD_CTL_HVE                     (1 << 13)
 91                  PAD_CTL_HYS                     (1 << 8)
 92                  PAD_CTL_PKE                     (1 << 7)
 93                  PAD_CTL_PUE                     (1 << 6)
 94                  PAD_CTL_PUS_100K_DOWN           (0 << 4)
 95                  PAD_CTL_PUS_47K_UP              (1 << 4)
 96                  PAD_CTL_PUS_100K_UP             (2 << 4)
 97                  PAD_CTL_PUS_22K_UP              (3 << 4)
 98                  PAD_CTL_ODE                     (1 << 3)
 99                  PAD_CTL_DSE_LOW                 (0 << 1)
100                  PAD_CTL_DSE_MED                 (1 << 1)
101                  PAD_CTL_DSE_HIGH                (2 << 1)
102                  PAD_CTL_DSE_MAX                 (3 << 1)
103                  PAD_CTL_SRE_FAST                (1 << 0)
104                  PAD_CTL_SRE_SLOW                (0 << 0)
105                Common i.MX6 bits
106                  PAD_CTL_HYS                     (1 << 16)
107                  PAD_CTL_PUS_100K_DOWN           (0 << 14)
108                  PAD_CTL_PUS_47K_UP              (1 << 14)
109                  PAD_CTL_PUS_100K_UP             (2 << 14)
110                  PAD_CTL_PUS_22K_UP              (3 << 14)
111                  PAD_CTL_PUE                     (1 << 13)
112                  PAD_CTL_PKE                     (1 << 12)
113                  PAD_CTL_ODE                     (1 << 11)
114                  PAD_CTL_SPEED_LOW               (0 << 6)
115                  PAD_CTL_SPEED_MED               (1 << 6)
116                  PAD_CTL_SPEED_HIGH              (3 << 6)
117                  PAD_CTL_DSE_DISABLE             (0 << 3)
118                  PAD_CTL_SRE_FAST                (1 << 0)
119                  PAD_CTL_SRE_SLOW                (0 << 0)
120                i.MX6SL/MX6SLL specific bits
121                  PAD_CTL_LVE                     (1 << 22) (MX6SL/SLL only)
122                i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits
123                  PAD_CTL_DSE_260ohm              (1 << 3)
124                  PAD_CTL_DSE_130ohm              (2 << 3)
125                  PAD_CTL_DSE_87ohm               (3 << 3)
126                  PAD_CTL_DSE_65ohm               (4 << 3)
127                  PAD_CTL_DSE_52ohm               (5 << 3)
128                  PAD_CTL_DSE_43ohm               (6 << 3)
129                  PAD_CTL_DSE_37ohm               (7 << 3)
130                i.MX6DL/i.MX6Q/i.MX6SL specific bits
131                  PAD_CTL_DSE_240ohm              (1 << 3)
132                  PAD_CTL_DSE_120ohm              (2 << 3)
133                  PAD_CTL_DSE_80ohm               (3 << 3)
134                  PAD_CTL_DSE_60ohm               (4 << 3)
135                  PAD_CTL_DSE_48ohm               (5 << 3)
136                  PAD_CTL_DSE_40ohm               (6 << 3)
137                  PAD_CTL_DSE_34ohm               (7 << 3)
138
139    required:
140      - fsl,pins
141
142    additionalProperties: false
143
144required:
145  - compatible
146  - reg
147
148additionalProperties: false
149
150examples:
151  - |
152    iomuxc: pinctrl@20e0000 {
153      compatible = "fsl,imx6ul-iomuxc";
154      reg = <0x020e0000 0x4000>;
155
156      mux_uart: uartgrp {
157        fsl,pins = <
158          0x0084 0x0310 0x0000 0 0 0x1b0b1
159          0x0088 0x0314 0x0624 0 3 0x1b0b1
160        >;
161      };
162    };
163  - |
164    iomuxc_snvs: pinctrl@2290000 {
165      compatible = "fsl,imx6ull-iomuxc-snvs";
166      reg = <0x02290000 0x4000>;
167
168      pinctrl_snvs_usbc_det: snvsusbcdetgrp {
169        fsl,pins = <
170          0x0010 0x0054 0x0000 0x5 0x0 0x130b0
171        >;
172      };
173    };
174  - |
175    iomuxc_mx6q: pinctrl@20e0000 {
176        compatible = "fsl,imx6q-iomuxc";
177        reg = <0x20e0000 0x4000>;
178
179        pinctrl_uart4: uart4grp {
180            fsl,pins =
181                <0x288 0x658 0x000 0x3 0x0	0x140>,
182                <0x28c 0x65c 0x938 0x3 0x3	0x140>;
183        };
184    };