brcm,ns2-pinmux.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/brcm,ns2-pinmux.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Broadcom Northstar2 IOMUX Controller
  8
  9maintainers:
 10  - Ray Jui <rjui@broadcom.com>
 11  - Scott Branden <sbranden@broadcom.com>
 12
 13properties:
 14  compatible:
 15    const: brcm,ns2-pinmux
 16
 17  reg:
 18    maxItems: 3
 19
 20additionalProperties:
 21  description: Pin group node properties
 22  type: object
 23  allOf:
 24    - $ref: /schemas/pinctrl/pincfg-node.yaml#
 25    - $ref: /schemas/pinctrl/pinmux-node.yaml#
 26  additionalProperties: false
 27
 28  properties:
 29    function:
 30      description: The mux function to select
 31      $ref: /schemas/types.yaml#/definitions/string
 32
 33    groups:
 34      items:
 35        enum: [
 36          nand_grp, nor_data_grp, nor_adv_grp, nor_addr_0_3_grp,
 37          nor_addr_4_5_grp, nor_addr_6_7_grp, nor_addr_8_9_grp,
 38          nor_addr_10_11_grp, nor_addr_12_15_grp, gpio_0_1_grp, gpio_2_5_grp,
 39          gpio_6_7_grp, gpio_8_9_grp, gpio_10_11_grp, gpio_12_13_grp,
 40          gpio_14_17_grp, gpio_18_19_grp, gpio_20_21_grp, gpio_22_23_grp,
 41          gpio_24_25_grp, gpio_26_27_grp, gpio_28_29_grp, gpio_30_31_grp,
 42          pcie_ab1_clk_wak_grp, pcie_a3_clk_wak_grp, pcie_b3_clk_wak_grp,
 43          pcie_b2_clk_wak_grp, pcie_a2_clk_wak_grp, uart0_modem_grp,
 44          uart0_rts_cts_grp, uart0_in_out_grp, uart1_ext_clk_grp,
 45          uart1_dcd_dsr_grp, uart1_ri_dtr_grp, uart1_rts_cts_grp,
 46          uart1_in_out_grp, uart2_rts_cts_grp, pwm_0_grp, pwm_1_grp, pwm_2_grp,
 47          pwm_3_grp
 48        ]
 49
 50    pins:
 51      items:
 52        enum: [
 53          qspi_wp, qspi_hold, qspi_cs, qspi_sck, uart3_sin, uart3_sout,
 54          qspi_mosi, qspi_miso, spi0_fss, spi0_rxd, spi0_txd, spi0_sck,
 55          spi1_fss, spi1_rxd, spi1_txd, spi1_sck, sdio0_data7, sdio0_emmc_rst,
 56          sdio0_led_on, sdio0_wp, sdio0_data3, sdio0_data4, sdio0_data5,
 57          sdio0_data6, sdio0_cmd, sdio0_data0, sdio0_data1, sdio0_data2,
 58          sdio1_led_on, sdio1_wp, sdio0_cd_l, sdio0_clk, sdio1_data5,
 59          sdio1_data6, sdio1_data7, sdio1_emmc_rst, sdio1_data1, sdio1_data2,
 60          sdio1_data3, sdio1_data4, sdio1_cd_l, sdio1_clk, sdio1_cmd,
 61          sdio1_data0, ext_mdio_0, ext_mdc_0, usb3_p1_vbus_ppc,
 62          usb3_p1_overcurrent, usb3_p0_vbus_ppc, usb3_p0_overcurrent,
 63          usb2_presence_indication, usb2_vbus_present, usb2_vbus_ppc,
 64          usb2_overcurrent, sata_led1, sata_led0
 65        ]
 66
 67    bias-disable: true
 68    bias-pull-down: true
 69    bias-pull-up: true
 70    drive-strength: true
 71    slew-rate: true
 72    input-enable: true
 73    input-disable: true
 74
 75  oneOf:
 76    - required:
 77        - groups
 78        - function
 79    - required:
 80        - pins
 81
 82required:
 83  - compatible
 84  - reg
 85
 86examples:
 87  - |
 88    pinctrl@6501d130 {
 89        compatible = "brcm,ns2-pinmux";
 90        reg = <0x6501d130 0x08>,
 91              <0x660a0028 0x04>,
 92              <0x660009b0 0x40>;
 93
 94        /* Select nand function */
 95        nand-sel {
 96            function = "nand";
 97            groups = "nand_grp";
 98        };
 99
100        /* Pull up the uart3 rx pin */
101        uart3-rx {
102            pins = "uart3_sin";
103            bias-pull-up;
104        };
105
106        /* Set the drive strength of sdio d4 pin */
107        sdio0-d4 {
108            pins = "sdio0_data4";
109            drive-strength = <8>;
110        };
111    };