actions,s900-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/actions,s900-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Actions Semi S900 Pin Controller
  8
  9maintainers:
 10  - Manivannan Sadhasivam <mani@kernel.org>
 11
 12properties:
 13  compatible:
 14    const: actions,s900-pinctrl
 15
 16  reg:
 17    maxItems: 1
 18
 19  interrupts:
 20    maxItems: 6
 21    description: The interrupt outputs from the controller. There is one GPIO
 22      interrupt per GPIO bank. The number of interrupts listed depends on the
 23      number of GPIO banks on the SoC. The interrupts must be ordered by bank,
 24      starting with bank 0.
 25
 26  interrupt-controller: true
 27
 28  "#interrupt-cells":
 29    const: 2
 30
 31  clocks:
 32    maxItems: 1
 33
 34  gpio-controller: true
 35
 36  gpio-line-names:
 37    maxItems: 146
 38
 39  gpio-ranges: true
 40
 41  "#gpio-cells":
 42    const: 2
 43
 44required:
 45  - compatible
 46  - reg
 47  - interrupts
 48  - interrupt-controller
 49  - "#interrupt-cells"
 50  - clocks
 51  - gpio-controller
 52  - gpio-ranges
 53  - "#gpio-cells"
 54
 55additionalProperties:
 56  type: object
 57  description: Pin configuration subnode
 58  additionalProperties: false
 59
 60  properties:
 61    pinmux:
 62      type: object
 63      description: Pin mux configuration
 64      $ref: /schemas/pinctrl/pinmux-node.yaml#
 65      additionalProperties: false
 66
 67      properties:
 68        groups:
 69          items:
 70            enum: [
 71              lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
 72              sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
 73              rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
 74              rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
 75              i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, pcm1_clk_mfp,
 76              pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, eram_a7_mfp, eram_a8_mfp,
 77              eram_a9_mfp, eram_a10_mfp, eram_a11_mfp, lvds_oep_odn_mfp,
 78              lvds_ocp_obn_mfp, lvds_oap_oan_mfp, lvds_e_mfp,
 79              spi0_sclk_mosi_mfp, spi0_ss_mfp, spi0_miso_mfp, uart2_rtsb_mfp,
 80              uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp,
 81              sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp,
 82              sd0_clk_mfp, sd1_cmd_clk_mfp, uart0_rx_mfp, nand0_d0_ceb3_mfp,
 83              uart0_tx_mfp, i2c0_mfp, csi0_cn_cp_mfp, csi0_dn0_dp3_mfp,
 84              csi1_dn0_cp_mfp, dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
 85              nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
 86              csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
 87            ]
 88
 89        function:
 90          items:
 91            enum: [
 92              eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
 93              uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
 94              pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
 95              sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
 96              usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
 97              nand1, spdif, sirq0, sirq1, sirq2
 98            ]
 99
100      required:
101        - groups
102        - function
103
104    pinconf:
105      type: object
106      description: Pin configuration parameters
107      allOf:
108        - $ref: /schemas/pinctrl/pincfg-node.yaml#
109        - $ref: /schemas/pinctrl/pinmux-node.yaml#
110
111      additionalProperties: false
112
113      properties:
114        groups:
115          items:
116            enum: [
117              # pin groups for drive strength
118              sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, rmii_tx_d0_d1_drv,
119              rmii_txen_rxer_drv, rmii_crs_dv_drv, rmii_rx_d1_d0_drv,
120              rmii_ref_clk_drv, rmii_mdc_mdio_drv, sirq_0_1_drv, sirq2_drv,
121              i2s_d0_d1_drv, i2s_lr_m_clk0_drv, i2s_blk1_mclk1_drv,
122              pcm1_in_out_drv, lvds_oap_oan_drv, lvds_oep_odn_drv,
123              lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, sd1_d3_d0_drv,
124              sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, spi0_ss_miso_drv,
125              uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, uart3_drv, i2c0_drv,
126              i2c1_drv, i2c2_drv, sensor0_drv,
127              # pin groups for slew rate
128              sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
129              rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
130              rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
131              i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
132              pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
133              spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
134              uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
135              sensor0_sr
136            ]
137
138        pins:
139          items:
140            enum: [
141              eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1,
142              eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2,
143              i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1,
144              i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out,
145              eram_a5, eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
146              lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn,
147              lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een,
148              lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn,
149              lvds_eap, lvds_ean, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
150              sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
151              spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, uart0_tx,
152              uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
153              uart3_rtsb, uart3_ctsb, uart4_rx, uart4_tx, i2c0_sclk, i2c0_sdata,
154              i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0,
155              csi0_dn1, csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2,
156              csi0_dn3, csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
157              dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
158              csi1_dn0, csi1_dp0, csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
159              sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, nand0_d4,
160              nand0_d5, nand0_d6, nand0_d7, nand0_dqs, nand0_dqsn, nand0_ale,
161              nand0_cle, nand0_ceb0, nand0_ceb1, nand0_ceb2, nand0_ceb3,
162              nand1_d0, nand1_d1, nand1_d2, nand1_d3, nand1_d4, nand1_d5,
163              nand1_d6, nand1_d7, nand1_dqs, nand1_dqsn, nand1_ale, nand1_cle,
164              nand1_ceb0, nand1_ceb1, nand1_ceb2, nand1_ceb3, sgpio0, sgpio1,
165              sgpio2, sgpio3
166            ]
167
168        bias-bus-hold: true
169        bias-high-impedance: true
170
171        bias-pull-down:
172          type: boolean
173
174        bias-pull-up:
175          type: boolean
176
177        input-schmitt-enable: true
178        input-schmitt-disable: true
179        slew-rate: true
180        drive-strength: true
181
182      oneOf:
183        - required:
184            - groups
185        - required:
186            - pins
187
188examples:
189  - |
190    #include <dt-bindings/interrupt-controller/arm-gic.h>
191
192    pinctrl: pinctrl@e01b0000 {
193        compatible = "actions,s900-pinctrl";
194        reg = <0xe01b0000 0x1000>;
195        clocks = <&cmu 1>;
196        gpio-controller;
197        gpio-ranges = <&pinctrl 0 0 146>;
198        #gpio-cells = <2>;
199        interrupt-controller;
200        #interrupt-cells = <2>;
201        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
202                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
203                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
204                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
205                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
206                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
207
208        uart2-default {
209            pinmux {
210                groups = "lvds_oep_odn_mfp";
211                function = "uart2";
212            };
213
214            pinconf {
215                groups = "lvds_oep_odn_drv";
216                drive-strength = <12>;
217            };
218        };
219    };