rockchip-inno-csi-dphy.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip SoC MIPI RX0 D-PHY
  8
  9maintainers:
 10  - Heiko Stuebner <heiko@sntech.de>
 11
 12description: |
 13  The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
 14  connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - rockchip,px30-csi-dphy
 20      - rockchip,rk1808-csi-dphy
 21      - rockchip,rk3326-csi-dphy
 22      - rockchip,rk3368-csi-dphy
 23      - rockchip,rk3568-csi-dphy
 24      - rockchip,rk3588-csi-dphy
 25
 26  reg:
 27    maxItems: 1
 28
 29  clocks:
 30    maxItems: 1
 31
 32  clock-names:
 33    const: pclk
 34
 35  '#phy-cells':
 36    const: 0
 37
 38  power-domains:
 39    description: Video in/out power domain.
 40    maxItems: 1
 41
 42  resets:
 43    items:
 44      - description: APB reset line
 45      - description: PHY reset line
 46    minItems: 1
 47
 48  reset-names:
 49    items:
 50      - const: apb
 51      - const: phy
 52    minItems: 1
 53
 54  rockchip,grf:
 55    $ref: /schemas/types.yaml#/definitions/phandle
 56    description:
 57      Some additional phy settings are access through GRF regs.
 58
 59required:
 60  - compatible
 61  - reg
 62  - clocks
 63  - clock-names
 64  - '#phy-cells'
 65  - resets
 66  - reset-names
 67  - rockchip,grf
 68
 69allOf:
 70  - if:
 71      properties:
 72        compatible:
 73          contains:
 74            enum:
 75              - rockchip,px30-csi-dphy
 76              - rockchip,rk1808-csi-dphy
 77              - rockchip,rk3326-csi-dphy
 78              - rockchip,rk3368-csi-dphy
 79    then:
 80      required:
 81        - power-domains
 82  - if:
 83      properties:
 84        compatible:
 85          contains:
 86            enum:
 87              - rockchip,px30-csi-dphy
 88              - rockchip,rk1808-csi-dphy
 89              - rockchip,rk3326-csi-dphy
 90              - rockchip,rk3368-csi-dphy
 91              - rockchip,rk3568-csi-dphy
 92    then:
 93      properties:
 94        resets:
 95          maxItems: 1
 96
 97        reset-names:
 98          maxItems: 1
 99    else:
100      properties:
101        resets:
102          minItems: 2
103
104        reset-names:
105          minItems: 2
106
107additionalProperties: false
108
109examples:
110  - |
111
112    csi_dphy: phy@ff2f0000 {
113        compatible = "rockchip,px30-csi-dphy";
114        reg = <0xff2f0000 0x4000>;
115        clocks = <&cru 1>;
116        clock-names = "pclk";
117        #phy-cells = <0>;
118        power-domains = <&power 1>;
119        resets = <&cru 1>;
120        reset-names = "apb";
121        rockchip,grf = <&grf>;
122    };
123  - |
124    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
125    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
126
127    soc {
128        #address-cells = <2>;
129        #size-cells = <2>;
130
131        phy@fedc0000 {
132            compatible = "rockchip,rk3588-csi-dphy";
133            reg = <0x0 0xfedc0000 0x0 0x8000>;
134            clocks = <&cru PCLK_CSIPHY0>;
135            clock-names = "pclk";
136            #phy-cells = <0>;
137            resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
138            reset-names = "apb", "phy";
139            rockchip,grf = <&csidphy0_grf>;
140        };
141    };