rockchip,rk3399-typec-phy.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/phy/rockchip,rk3399-typec-phy.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip Type-C PHY
  8
  9maintainers:
 10  - Heiko Stuebner <heiko@sntech.de>
 11
 12properties:
 13  compatible:
 14    const: rockchip,rk3399-typec-phy
 15
 16  reg:
 17    maxItems: 1
 18
 19  clocks:
 20    maxItems: 2
 21
 22  clock-names:
 23    items:
 24      - const: tcpdcore
 25      - const: tcpdphy-ref
 26
 27  extcon: true
 28
 29  power-domains:
 30    maxItems: 1
 31
 32  resets:
 33    maxItems: 3
 34
 35  reset-names:
 36    items:
 37      - const: uphy
 38      - const: uphy-pipe
 39      - const: uphy-tcphy
 40
 41  rockchip,grf:
 42    $ref: /schemas/types.yaml#/definitions/phandle
 43    description:
 44      Phandle to the syscon managing the "general register files" (GRF).
 45
 46  dp-port:
 47    type: object
 48    additionalProperties: false
 49
 50    properties:
 51      '#phy-cells':
 52        const: 0
 53
 54      port:
 55        $ref: /schemas/graph.yaml#/properties/port
 56        description: Connection to USB Type-C connector
 57
 58    required:
 59      - '#phy-cells'
 60
 61  usb3-port:
 62    type: object
 63    additionalProperties: false
 64
 65    properties:
 66      '#phy-cells':
 67        const: 0
 68
 69      orientation-switch: true
 70
 71      port:
 72        $ref: /schemas/graph.yaml#/properties/port
 73        description: Connection to USB Type-C connector SS port
 74
 75    required:
 76      - '#phy-cells'
 77
 78required:
 79  - compatible
 80  - reg
 81  - clocks
 82  - clock-names
 83  - resets
 84  - reset-names
 85  - dp-port
 86  - usb3-port
 87
 88additionalProperties: false
 89
 90examples:
 91  - |
 92    #include <dt-bindings/clock/rk3399-cru.h>
 93
 94    phy@ff7c0000 {
 95        compatible = "rockchip,rk3399-typec-phy";
 96        reg = <0xff7c0000 0x40000>;
 97        rockchip,grf = <&grf>;
 98        extcon = <&fusb0>;
 99        clocks = <&cru SCLK_UPHY0_TCPDCORE>,
100           <&cru SCLK_UPHY0_TCPDPHY_REF>;
101        clock-names = "tcpdcore", "tcpdphy-ref";
102        resets = <&cru SRST_UPHY0>,
103                 <&cru SRST_UPHY0_PIPE_L00>,
104                 <&cru SRST_P_UPHY0_TCPHY>;
105        reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
106
107        dp-port {
108            #phy-cells = <0>;
109        };
110
111        usb3-port {
112            #phy-cells = <0>;
113        };
114    };
115
116...