rockchip,px30-dsi-dphy.yaml

 1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Rockchip MIPI DPHY with additional LVDS/TTL modes
 8
 9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  "#phy-cells":
14    const: 0
15
16  compatible:
17    enum:
18      - rockchip,px30-dsi-dphy
19      - rockchip,rk3128-dsi-dphy
20      - rockchip,rk3368-dsi-dphy
21      - rockchip,rk3506-dsi-dphy
22      - rockchip,rk3568-dsi-dphy
23      - rockchip,rv1126-dsi-dphy
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    items:
30      - description: PLL reference clock
31      - description: Module clock
32
33  clock-names:
34    items:
35      - const: ref
36      - const: pclk
37
38  power-domains:
39    maxItems: 1
40    description: phandle to the associated power domain
41
42  resets:
43    items:
44      - description: exclusive PHY reset line
45
46  reset-names:
47    items:
48      - const: apb
49
50required:
51  - "#phy-cells"
52  - compatible
53  - reg
54  - clocks
55  - clock-names
56  - resets
57  - reset-names
58
59additionalProperties: false
60
61examples:
62  - |
63    dsi_dphy: phy@ff2e0000 {
64        compatible = "rockchip,px30-dsi-dphy";
65        reg = <0xff2e0000 0x10000>;
66        clocks = <&pmucru 13>, <&cru 12>;
67        clock-names = "ref", "pclk";
68        resets = <&cru 12>;
69        reset-names = "apb";
70        #phy-cells = <0>;
71    };
72
73...