qcom,sc8280xp-qmp-usb43dp-phy.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
  8
  9maintainers:
 10  - Vinod Koul <vkoul@kernel.org>
 11
 12description:
 13  The QMP PHY controller supports physical layer functionality for a number of
 14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - qcom,sar2130p-qmp-usb3-dp-phy
 20      - qcom,sc7180-qmp-usb3-dp-phy
 21      - qcom,sc7280-qmp-usb3-dp-phy
 22      - qcom,sc8180x-qmp-usb3-dp-phy
 23      - qcom,sc8280xp-qmp-usb43dp-phy
 24      - qcom,sdm845-qmp-usb3-dp-phy
 25      - qcom,sm6350-qmp-usb3-dp-phy
 26      - qcom,sm8150-qmp-usb3-dp-phy
 27      - qcom,sm8250-qmp-usb3-dp-phy
 28      - qcom,sm8350-qmp-usb3-dp-phy
 29      - qcom,sm8450-qmp-usb3-dp-phy
 30      - qcom,sm8550-qmp-usb3-dp-phy
 31      - qcom,sm8650-qmp-usb3-dp-phy
 32      - qcom,sm8750-qmp-usb3-dp-phy
 33      - qcom,x1e80100-qmp-usb3-dp-phy
 34
 35  reg:
 36    maxItems: 1
 37
 38  clocks:
 39    minItems: 4
 40    maxItems: 5
 41
 42  clock-names:
 43    minItems: 4
 44    items:
 45      - const: aux
 46      - const: ref
 47      - const: com_aux
 48      - const: usb3_pipe
 49      - const: cfg_ahb
 50
 51  power-domains:
 52    maxItems: 1
 53
 54  resets:
 55    maxItems: 2
 56
 57  reset-names:
 58    items:
 59      - const: phy
 60      - const: common
 61
 62  vdda-phy-supply: true
 63
 64  vdda-pll-supply: true
 65
 66  "#clock-cells":
 67    const: 1
 68    description:
 69      See include/dt-bindings/phy/phy-qcom-qmp.h
 70
 71  "#phy-cells":
 72    const: 1
 73    description:
 74      See include/dt-bindings/phy/phy-qcom-qmp.h
 75
 76  mode-switch: true
 77  orientation-switch: true
 78
 79  ports:
 80    $ref: /schemas/graph.yaml#/properties/ports
 81
 82    properties:
 83      port@0:
 84        $ref: /schemas/graph.yaml#/$defs/port-base
 85        description: Output endpoint of the PHY
 86        unevaluatedProperties: false
 87
 88        properties:
 89          endpoint:
 90            $ref: /schemas/graph.yaml#/$defs/endpoint-base
 91            unevaluatedProperties: false
 92
 93          endpoint@0:
 94            $ref: /schemas/graph.yaml#/$defs/endpoint-base
 95            description: Display Port Output lanes of the PHY when used with static mapping,
 96                         The entry index is the DP lanes index, and the number is the PHY
 97                         signal in the order RX0, TX0, TX1, RX1.
 98            unevaluatedProperties: false
 99
100            properties:
101              # Static lane mappings are mutually exclusive with typec-mux/orientation-mux
102              data-lanes:
103                $ref: /schemas/types.yaml#/definitions/uint32-array
104                minItems: 2
105                maxItems: 4
106                oneOf:
107                  - items: # DisplayPort 1 lane, normal orientation
108                      - const: 3
109                  - items: # DisplayPort 1 lane, flipped orientation
110                      - const: 0
111                  - items: # DisplayPort 2 lanes, normal orientation
112                      - const: 3
113                      - const: 2
114                  - items: # DisplayPort 2 lanes, flipped orientation
115                      - const: 0
116                      - const: 1
117                  - items: # DisplayPort 4 lanes, normal orientation
118                      - const: 3
119                      - const: 2
120                      - const: 1
121                      - const: 0
122                  - items: # DisplayPort 4 lanes, flipped orientation
123                      - const: 0
124                      - const: 1
125                      - const: 2
126                      - const: 3
127            required:
128              - data-lanes
129
130          endpoint@1:
131            $ref: /schemas/graph.yaml#/$defs/endpoint-base
132            description: USB Output lanes of the PHY when used with static mapping.
133                         The entry index is the USB3 lane in the order TX then RX, and the
134                         number is the PHY signal in the order RX0, TX0, TX1, RX1.
135            unevaluatedProperties: false
136
137            properties:
138              # Static lane mappings are mutually exclusive with typec-mux/orientation-mux
139              data-lanes:
140                $ref: /schemas/types.yaml#/definitions/uint32-array
141                minItems: 2
142                oneOf:
143                  - items: # USB3, normal orientation
144                      - const: 1
145                      - const: 0
146                  - items: # USB3, flipped orientation
147                      - const: 2
148                      - const: 3
149
150            required:
151              - data-lanes
152
153      port@1:
154        $ref: /schemas/graph.yaml#/properties/port
155        description: Incoming endpoint from the USB controller
156
157      port@2:
158        $ref: /schemas/graph.yaml#/properties/port
159        description: Incoming endpoint from the DisplayPort controller
160
161required:
162  - compatible
163  - reg
164  - clocks
165  - clock-names
166  - resets
167  - reset-names
168  - vdda-phy-supply
169  - vdda-pll-supply
170  - "#clock-cells"
171  - "#phy-cells"
172
173allOf:
174  - $ref: /schemas/usb/usb-switch.yaml#
175  - if:
176      properties:
177        compatible:
178          enum:
179            - qcom,sc7180-qmp-usb3-dp-phy
180            - qcom,sdm845-qmp-usb3-dp-phy
181    then:
182      properties:
183        clocks:
184          maxItems: 5
185        clock-names:
186          maxItems: 5
187    else:
188      properties:
189        clocks:
190          maxItems: 4
191        clock-names:
192          maxItems: 4
193
194  - if:
195      properties:
196        compatible:
197          enum:
198            - qcom,sar2130p-qmp-usb3-dp-phy
199            - qcom,sc8280xp-qmp-usb43dp-phy
200            - qcom,sm6350-qmp-usb3-dp-phy
201            - qcom,sm8550-qmp-usb3-dp-phy
202            - qcom,sm8650-qmp-usb3-dp-phy
203            - qcom,sm8750-qmp-usb3-dp-phy
204            - qcom,x1e80100-qmp-usb3-dp-phy
205    then:
206      required:
207        - power-domains
208    else:
209      properties:
210        power-domains: false
211
212additionalProperties: false
213
214examples:
215  - |
216    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
217
218    phy@88eb000 {
219      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
220      reg = <0x088eb000 0x4000>;
221
222      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
223               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
224               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
225               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
226      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
227
228      power-domains = <&gcc USB30_PRIM_GDSC>;
229
230      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
231               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
232      reset-names = "phy", "common";
233
234      vdda-phy-supply = <&vreg_l9d>;
235      vdda-pll-supply = <&vreg_l4d>;
236
237      orientation-switch;
238
239      #clock-cells = <1>;
240      #phy-cells = <1>;
241
242      ports {
243          #address-cells = <1>;
244          #size-cells = <0>;
245
246          port@0 {
247              reg = <0>;
248
249              endpoint {
250                  remote-endpoint = <&typec_connector_ss>;
251              };
252          };
253
254          port@1 {
255              reg = <1>;
256
257              endpoint {
258                  remote-endpoint = <&dwc3_ss_out>;
259              };
260          };
261
262          port@2 {
263              reg = <2>;
264
265              endpoint {
266                  remote-endpoint = <&mdss_dp_out>;
267              };
268          };
269      };
270    };