qcom,sc8280xp-qmp-pcie-phy.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
  8
  9maintainers:
 10  - Vinod Koul <vkoul@kernel.org>
 11
 12description:
 13  The QMP PHY controller supports physical layer functionality for a number of
 14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - qcom,glymur-qmp-gen5x4-pcie-phy
 20      - qcom,qcs615-qmp-gen3x1-pcie-phy
 21      - qcom,qcs8300-qmp-gen4x2-pcie-phy
 22      - qcom,sa8775p-qmp-gen4x2-pcie-phy
 23      - qcom,sa8775p-qmp-gen4x4-pcie-phy
 24      - qcom,sar2130p-qmp-gen3x2-pcie-phy
 25      - qcom,sc8180x-qmp-pcie-phy
 26      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
 27      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
 28      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
 29      - qcom,sdm845-qhp-pcie-phy
 30      - qcom,sdm845-qmp-pcie-phy
 31      - qcom,sdx55-qmp-pcie-phy
 32      - qcom,sdx65-qmp-gen4x2-pcie-phy
 33      - qcom,sm8150-qmp-gen3x1-pcie-phy
 34      - qcom,sm8150-qmp-gen3x2-pcie-phy
 35      - qcom,sm8250-qmp-gen3x1-pcie-phy
 36      - qcom,sm8250-qmp-gen3x2-pcie-phy
 37      - qcom,sm8250-qmp-modem-pcie-phy
 38      - qcom,sm8350-qmp-gen3x1-pcie-phy
 39      - qcom,sm8350-qmp-gen3x2-pcie-phy
 40      - qcom,sm8450-qmp-gen3x1-pcie-phy
 41      - qcom,sm8450-qmp-gen4x2-pcie-phy
 42      - qcom,sm8550-qmp-gen3x2-pcie-phy
 43      - qcom,sm8550-qmp-gen4x2-pcie-phy
 44      - qcom,sm8650-qmp-gen3x2-pcie-phy
 45      - qcom,sm8650-qmp-gen4x2-pcie-phy
 46      - qcom,sm8750-qmp-gen3x2-pcie-phy
 47      - qcom,x1e80100-qmp-gen3x2-pcie-phy
 48      - qcom,x1e80100-qmp-gen4x2-pcie-phy
 49      - qcom,x1e80100-qmp-gen4x4-pcie-phy
 50      - qcom,x1e80100-qmp-gen4x8-pcie-phy
 51      - qcom,x1p42100-qmp-gen4x4-pcie-phy
 52
 53  reg:
 54    minItems: 1
 55    maxItems: 2
 56
 57  clocks:
 58    minItems: 5
 59    maxItems: 6
 60
 61  clock-names:
 62    minItems: 5
 63    items:
 64      - const: aux
 65      - const: cfg_ahb
 66      - const: ref
 67      - enum: [rchng, refgen]
 68      - const: pipe
 69      - const: pipediv2
 70
 71  power-domains:
 72    maxItems: 1
 73
 74  resets:
 75    minItems: 1
 76    maxItems: 2
 77
 78  reset-names:
 79    minItems: 1
 80    items:
 81      - const: phy
 82      - const: phy_nocsr
 83
 84  vdda-phy-supply: true
 85
 86  vdda-pll-supply: true
 87
 88  vdda-qref-supply: true
 89
 90  qcom,4ln-config-sel:
 91    description: PCIe 4-lane configuration
 92    $ref: /schemas/types.yaml#/definitions/phandle-array
 93    items:
 94      - items:
 95          - description: phandle of TCSR syscon
 96          - description: offset of PCIe 4-lane configuration register
 97          - description: offset of configuration bit for this PHY
 98
 99  "#clock-cells": true
100
101  clock-output-names:
102    maxItems: 1
103
104  "#phy-cells":
105    const: 0
106
107required:
108  - compatible
109  - reg
110  - clocks
111  - clock-names
112  - resets
113  - reset-names
114  - vdda-phy-supply
115  - vdda-pll-supply
116  - "#clock-cells"
117  - clock-output-names
118  - "#phy-cells"
119
120additionalProperties: false
121
122allOf:
123  - if:
124      properties:
125        compatible:
126          contains:
127            enum:
128              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
129              - qcom,x1e80100-qmp-gen4x4-pcie-phy
130              - qcom,x1p42100-qmp-gen4x4-pcie-phy
131    then:
132      properties:
133        reg:
134          items:
135            - description: port a
136            - description: port b
137      required:
138        - qcom,4ln-config-sel
139    else:
140      properties:
141        reg:
142          maxItems: 1
143
144  - if:
145      properties:
146        compatible:
147          contains:
148            enum:
149              - qcom,qcs615-qmp-gen3x1-pcie-phy
150              - qcom,sar2130p-qmp-gen3x2-pcie-phy
151              - qcom,sc8180x-qmp-pcie-phy
152              - qcom,sdm845-qhp-pcie-phy
153              - qcom,sdm845-qmp-pcie-phy
154              - qcom,sdx55-qmp-pcie-phy
155              - qcom,sm8150-qmp-gen3x1-pcie-phy
156              - qcom,sm8150-qmp-gen3x2-pcie-phy
157              - qcom,sm8250-qmp-gen3x1-pcie-phy
158              - qcom,sm8250-qmp-gen3x2-pcie-phy
159              - qcom,sm8250-qmp-modem-pcie-phy
160              - qcom,sm8350-qmp-gen3x1-pcie-phy
161              - qcom,sm8350-qmp-gen3x2-pcie-phy
162              - qcom,sm8450-qmp-gen3x1-pcie-phy
163              - qcom,sm8450-qmp-gen3x2-pcie-phy
164              - qcom,sm8550-qmp-gen3x2-pcie-phy
165              - qcom,sm8550-qmp-gen4x2-pcie-phy
166              - qcom,sm8650-qmp-gen3x2-pcie-phy
167              - qcom,sm8650-qmp-gen4x2-pcie-phy
168              - qcom,sm8750-qmp-gen3x2-pcie-phy
169    then:
170      properties:
171        clocks:
172          maxItems: 5
173        clock-names:
174          maxItems: 5
175
176  - if:
177      properties:
178        compatible:
179          contains:
180            enum:
181              - qcom,glymur-qmp-gen5x4-pcie-phy
182              - qcom,qcs8300-qmp-gen4x2-pcie-phy
183              - qcom,sa8775p-qmp-gen4x2-pcie-phy
184              - qcom,sa8775p-qmp-gen4x4-pcie-phy
185              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
186              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
187              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
188              - qcom,x1e80100-qmp-gen3x2-pcie-phy
189              - qcom,x1e80100-qmp-gen4x2-pcie-phy
190              - qcom,x1e80100-qmp-gen4x4-pcie-phy
191              - qcom,x1e80100-qmp-gen4x8-pcie-phy
192              - qcom,x1p42100-qmp-gen4x4-pcie-phy
193    then:
194      properties:
195        clocks:
196          minItems: 6
197        clock-names:
198          minItems: 6
199
200  - if:
201      properties:
202        compatible:
203          contains:
204            enum:
205              - qcom,glymur-qmp-gen5x4-pcie-phy
206              - qcom,sm8550-qmp-gen4x2-pcie-phy
207              - qcom,sm8650-qmp-gen4x2-pcie-phy
208              - qcom,x1e80100-qmp-gen3x2-pcie-phy
209              - qcom,x1e80100-qmp-gen4x2-pcie-phy
210              - qcom,x1e80100-qmp-gen4x4-pcie-phy
211              - qcom,x1e80100-qmp-gen4x8-pcie-phy
212              - qcom,x1p42100-qmp-gen4x4-pcie-phy
213    then:
214      properties:
215        resets:
216          minItems: 2
217        reset-names:
218          minItems: 2
219    else:
220      properties:
221        resets:
222          maxItems: 1
223        reset-names:
224          maxItems: 1
225
226  - if:
227      properties:
228        compatible:
229          contains:
230            enum:
231              - qcom,sm8450-qmp-gen4x2-pcie-phy
232              - qcom,sm8550-qmp-gen4x2-pcie-phy
233              - qcom,sm8650-qmp-gen4x2-pcie-phy
234    then:
235      properties:
236        "#clock-cells":
237          const: 1
238    else:
239      properties:
240        "#clock-cells":
241          const: 0
242
243examples:
244  - |
245    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
246
247    pcie2b_phy: phy@1c18000 {
248      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
249      reg = <0x01c18000 0x2000>;
250
251      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
252               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
253               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
254               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
255               <&gcc GCC_PCIE_2B_PIPE_CLK>,
256               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
257      clock-names = "aux", "cfg_ahb", "ref", "rchng",
258                    "pipe", "pipediv2";
259
260      power-domains = <&gcc PCIE_2B_GDSC>;
261
262      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
263      reset-names = "phy";
264
265      vdda-phy-supply = <&vreg_l6d>;
266      vdda-pll-supply = <&vreg_l4d>;
267
268      #clock-cells = <0>;
269      clock-output-names = "pcie_2b_pipe_clk";
270
271      #phy-cells = <0>;
272    };
273
274    pcie2a_phy: phy@1c24000 {
275      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
276      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
277
278      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
279               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
280               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
281               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
282               <&gcc GCC_PCIE_2A_PIPE_CLK>,
283               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
284      clock-names = "aux", "cfg_ahb", "ref", "rchng",
285                    "pipe", "pipediv2";
286
287      power-domains = <&gcc PCIE_2A_GDSC>;
288
289      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
290      reset-names = "phy";
291
292      vdda-phy-supply = <&vreg_l6d>;
293      vdda-pll-supply = <&vreg_l4d>;
294
295      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
296
297      #clock-cells = <0>;
298      clock-output-names = "pcie_2a_pipe_clk";
299
300      #phy-cells = <0>;
301    };