qcom,ipq5332-uniphy-pcie-phy.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm UNIPHY PCIe 28LP PHY
  8
  9maintainers:
 10  - Nitheesh Sekar <quic_nsekar@quicinc.com>
 11  - Varadarajan Narayanan <quic_varada@quicinc.com>
 12
 13description:
 14  PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs
 15
 16properties:
 17  compatible:
 18    enum:
 19      - qcom,ipq5018-uniphy-pcie-phy
 20      - qcom,ipq5332-uniphy-pcie-phy
 21
 22  reg:
 23    maxItems: 1
 24
 25  clocks:
 26    minItems: 1
 27    maxItems: 2
 28
 29  resets:
 30    minItems: 2
 31    maxItems: 3
 32
 33  "#phy-cells":
 34    const: 0
 35
 36  "#clock-cells":
 37    const: 0
 38
 39  num-lanes:
 40    $ref: /schemas/types.yaml#/definitions/uint32
 41    enum: [1, 2]
 42
 43required:
 44  - compatible
 45  - reg
 46  - clocks
 47  - resets
 48  - "#phy-cells"
 49  - "#clock-cells"
 50  - num-lanes
 51
 52additionalProperties: false
 53
 54allOf:
 55  - if:
 56      properties:
 57        compatible:
 58          contains:
 59            enum:
 60              - qcom,ipq5018-uniphy-pcie-phy
 61    then:
 62      properties:
 63        clocks:
 64          items:
 65            - description: pcie pipe clock
 66        resets:
 67          items:
 68            - description: phy reset
 69            - description: cfg reset
 70
 71  - if:
 72      properties:
 73        compatible:
 74          contains:
 75            enum:
 76              - qcom,ipq5332-uniphy-pcie-phy
 77    then:
 78      properties:
 79        clocks:
 80          items:
 81            - description: pcie pipe clock
 82            - description: pcie ahb clock
 83        resets:
 84          items:
 85            - description: phy reset
 86            - description: ahb reset
 87            - description: cfg reset
 88
 89examples:
 90  - |
 91    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
 92
 93    pcie0_phy: phy@4b0000 {
 94        compatible = "qcom,ipq5332-uniphy-pcie-phy";
 95        reg = <0x004b0000 0x800>;
 96
 97        clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
 98                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
 99
100        resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
101                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
102                 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
103
104        #clock-cells = <0>;
105
106        #phy-cells = <0>;
107
108        num-lanes = <1>;
109    };