phy-rockchip-usbdp.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip USBDP Combo PHY with Samsung IP block
  8
  9maintainers:
 10  - Frank Wang <frank.wang@rock-chips.com>
 11  - Zhang Yubing <yubing.zhang@rock-chips.com>
 12
 13properties:
 14  compatible:
 15    enum:
 16      - rockchip,rk3576-usbdp-phy
 17      - rockchip,rk3588-usbdp-phy
 18
 19  reg:
 20    maxItems: 1
 21
 22  "#phy-cells":
 23    description: |
 24      Cell allows setting the type of the PHY. Possible values are:
 25      - PHY_TYPE_USB3
 26      - PHY_TYPE_DP
 27    const: 1
 28
 29  clocks:
 30    maxItems: 4
 31
 32  clock-names:
 33    items:
 34      - const: refclk
 35      - const: immortal
 36      - const: pclk
 37      - const: utmi
 38
 39  resets:
 40    maxItems: 5
 41
 42  reset-names:
 43    items:
 44      - const: init
 45      - const: cmn
 46      - const: lane
 47      - const: pcs_apb
 48      - const: pma_apb
 49
 50  phy-supply:
 51    description: Single PHY regulator
 52
 53  rockchip,dp-lane-mux:
 54    $ref: /schemas/types.yaml#/definitions/uint32-array
 55    minItems: 2
 56    maxItems: 4
 57    items:
 58      maximum: 3
 59    description:
 60      An array of physical Type-C lanes indexes. Position of an entry
 61      determines the DisplayPort (DP) lane index, while the value of an entry
 62      indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
 63      e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
 64      3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
 65      lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
 66      <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
 67      phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
 68      DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
 69
 70  rockchip,u2phy-grf:
 71    $ref: /schemas/types.yaml#/definitions/phandle
 72    description:
 73      Phandle to the syscon managing the 'usb2 phy general register files'.
 74
 75  rockchip,usb-grf:
 76    $ref: /schemas/types.yaml#/definitions/phandle
 77    description:
 78      Phandle to the syscon managing the 'usb general register files'.
 79
 80  rockchip,usbdpphy-grf:
 81    $ref: /schemas/types.yaml#/definitions/phandle
 82    description:
 83      Phandle to the syscon managing the 'usbdp phy general register files'.
 84
 85  rockchip,vo-grf:
 86    $ref: /schemas/types.yaml#/definitions/phandle
 87    description:
 88      Phandle to the syscon managing the 'video output general register files'.
 89      When select the DP lane mapping will request its phandle.
 90
 91  sbu1-dc-gpios:
 92    description:
 93      GPIO connected to the SBU1 line of the USB-C connector via a big resistor
 94      (~100K) to apply a DC offset for signalling the connector orientation.
 95    maxItems: 1
 96
 97  sbu2-dc-gpios:
 98    description:
 99      GPIO connected to the SBU2 line of the USB-C connector via a big resistor
100      (~100K) to apply a DC offset for signalling the connector orientation.
101    maxItems: 1
102
103  orientation-switch:
104    description: Flag the port as possible handler of orientation switching
105    type: boolean
106
107  mode-switch:
108    description: Flag the port as possible handler of altmode switching
109    type: boolean
110
111  port:
112    $ref: /schemas/graph.yaml#/properties/port
113    description:
114      A port node to link the PHY to a TypeC controller for the purpose of
115      handling orientation switching.
116
117required:
118  - compatible
119  - reg
120  - clocks
121  - clock-names
122  - resets
123  - reset-names
124  - "#phy-cells"
125
126additionalProperties: false
127
128examples:
129  - |
130    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
131    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
132
133    usbdp_phy0: phy@fed80000 {
134      compatible = "rockchip,rk3588-usbdp-phy";
135      reg = <0xfed80000 0x10000>;
136      #phy-cells = <1>;
137      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
138               <&cru CLK_USBDP_PHY0_IMMORTAL>,
139               <&cru PCLK_USBDPPHY0>,
140               <&u2phy0>;
141      clock-names = "refclk", "immortal", "pclk", "utmi";
142      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
143               <&cru SRST_USBDP_COMBO_PHY0_CMN>,
144               <&cru SRST_USBDP_COMBO_PHY0_LANE>,
145               <&cru SRST_USBDP_COMBO_PHY0_PCS>,
146               <&cru SRST_P_USBDPPHY0>;
147      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
148      rockchip,u2phy-grf = <&usb2phy0_grf>;
149      rockchip,usb-grf = <&usb_grf>;
150      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
151      rockchip,vo-grf = <&vo0_grf>;
152    };