apm,xgene-pmu.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/perf/apm,xgene-pmu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: APM X-Gene SoC PMU
  8
  9maintainers:
 10  - Khuong Dinh <khuong@os.amperecomputing.com>
 11
 12description: |
 13  This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
 14  The following PMU devices are supported:
 15
 16    L3C            - L3 cache controller
 17    IOB            - IO bridge
 18    MCB            - Memory controller bridge
 19    MC             - Memory controller
 20
 21properties:
 22  compatible:
 23    enum:
 24      - apm,xgene-pmu
 25      - apm,xgene-pmu-v2
 26
 27  "#address-cells":
 28    const: 2
 29
 30  "#size-cells":
 31    const: 2
 32
 33  ranges: true
 34
 35  reg:
 36    maxItems: 1
 37
 38  interrupts:
 39    maxItems: 1
 40
 41  regmap-csw:
 42    $ref: /schemas/types.yaml#/definitions/phandle
 43
 44  regmap-mcba:
 45    $ref: /schemas/types.yaml#/definitions/phandle
 46
 47  regmap-mcbb:
 48    $ref: /schemas/types.yaml#/definitions/phandle
 49
 50required:
 51  - compatible
 52  - regmap-csw
 53  - regmap-mcba
 54  - regmap-mcbb
 55  - reg
 56  - interrupts
 57
 58additionalProperties:
 59  type: object
 60  additionalProperties: false
 61
 62  properties:
 63    compatible:
 64      enum:
 65        - apm,xgene-pmu-l3c
 66        - apm,xgene-pmu-iob
 67        - apm,xgene-pmu-mcb
 68        - apm,xgene-pmu-mc
 69
 70    reg:
 71      maxItems: 1
 72
 73    enable-bit-index:
 74      description:
 75        Specifies which bit enables the associated resource in MCB or MC subnodes.
 76      $ref: /schemas/types.yaml#/definitions/uint32
 77      maximum: 31
 78
 79examples:
 80  - |
 81    bus {
 82        #address-cells = <2>;
 83        #size-cells = <2>;
 84
 85        pmu@78810000 {
 86            compatible = "apm,xgene-pmu-v2";
 87            reg = <0x0 0x78810000 0x0 0x1000>;
 88            #address-cells = <2>;
 89            #size-cells = <2>;
 90            ranges;
 91            regmap-csw = <&csw>;
 92            regmap-mcba = <&mcba>;
 93            regmap-mcbb = <&mcbb>;
 94            interrupts = <0x0 0x22 0x4>;
 95
 96            pmul3c@7e610000 {
 97                compatible = "apm,xgene-pmu-l3c";
 98                reg = <0x0 0x7e610000 0x0 0x1000>;
 99            };
100
101            pmuiob@7e940000 {
102                compatible = "apm,xgene-pmu-iob";
103                reg = <0x0 0x7e940000 0x0 0x1000>;
104            };
105
106            pmucmcb@7e710000 {
107                compatible = "apm,xgene-pmu-mcb";
108                reg = <0x0 0x7e710000 0x0 0x1000>;
109                enable-bit-index = <0>;
110            };
111
112            pmucmcb@7e730000 {
113                compatible = "apm,xgene-pmu-mcb";
114                reg = <0x0 0x7e730000 0x0 0x1000>;
115                enable-bit-index = <1>;
116            };
117
118            pmucmc@7e810000 {
119                compatible = "apm,xgene-pmu-mc";
120                reg = <0x0 0x7e810000 0x0 0x1000>;
121                enable-bit-index = <0>;
122            };
123
124            pmucmc@7e850000 {
125                compatible = "apm,xgene-pmu-mc";
126                reg = <0x0 0x7e850000 0x0 0x1000>;
127                enable-bit-index = <1>;
128            };
129
130            pmucmc@7e890000 {
131                compatible = "apm,xgene-pmu-mc";
132                reg = <0x0 0x7e890000 0x0 0x1000>;
133                enable-bit-index = <2>;
134            };
135
136            pmucmc@7e8d0000 {
137                compatible = "apm,xgene-pmu-mc";
138                reg = <0x0 0x7e8d0000 0x0 0x1000>;
139                enable-bit-index = <3>;
140            };
141        };
142    };