xlnx,nwl-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Xilinx NWL PCIe Root Port Bridge
  8
  9maintainers:
 10  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
 11
 12allOf:
 13  - $ref: /schemas/pci/pci-host-bridge.yaml#
 14  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
 15
 16properties:
 17  compatible:
 18    const: xlnx,nwl-pcie-2.11
 19
 20  reg:
 21    items:
 22      - description: PCIe bridge registers location.
 23      - description: PCIe Controller registers location.
 24      - description: PCIe Configuration space region.
 25
 26  reg-names:
 27    items:
 28      - const: breg
 29      - const: pcireg
 30      - const: cfg
 31
 32  interrupts:
 33    items:
 34      - description: interrupt asserted when miscellaneous interrupt is received
 35      - description: unused interrupt(dummy)
 36      - description: interrupt asserted when a legacy interrupt is received
 37      - description: msi1 interrupt asserted when an MSI is received
 38      - description: msi0 interrupt asserted when an MSI is received
 39
 40  interrupt-names:
 41    items:
 42      - const: misc
 43      - const: dummy
 44      - const: intx
 45      - const: msi1
 46      - const: msi0
 47
 48  interrupt-map-mask:
 49    items:
 50      - const: 0
 51      - const: 0
 52      - const: 0
 53      - const: 7
 54
 55  "#interrupt-cells":
 56    const: 1
 57
 58  msi-parent:
 59    description: MSI controller the device is capable of using.
 60
 61  interrupt-map:
 62    maxItems: 4
 63
 64  phys:
 65    minItems: 1
 66    maxItems: 4
 67    description: One phy per logical lane, in order
 68
 69  power-domains:
 70    maxItems: 1
 71
 72  iommus:
 73    maxItems: 1
 74
 75  dma-coherent:
 76    description: optional, only needed if DMA operations are coherent.
 77
 78  clocks:
 79    maxItems: 1
 80    description: optional, input clock specifier.
 81
 82  legacy-interrupt-controller:
 83    description: Interrupt controller node for handling legacy PCI interrupts.
 84    type: object
 85    properties:
 86      "#address-cells":
 87        const: 0
 88
 89      "#interrupt-cells":
 90        const: 1
 91
 92      interrupt-controller: true
 93
 94    required:
 95      - "#address-cells"
 96      - "#interrupt-cells"
 97      - interrupt-controller
 98
 99    additionalProperties: false
100
101required:
102  - compatible
103  - reg
104  - reg-names
105  - interrupts
106  - "#interrupt-cells"
107  - interrupt-map
108  - interrupt-map-mask
109  - msi-controller
110  - power-domains
111
112unevaluatedProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/interrupt-controller/arm-gic.h>
117    #include <dt-bindings/interrupt-controller/irq.h>
118    #include <dt-bindings/phy/phy.h>
119    #include <dt-bindings/power/xlnx-zynqmp-power.h>
120    soc {
121        #address-cells = <2>;
122        #size-cells = <2>;
123        nwl_pcie: pcie@fd0e0000 {
124            compatible = "xlnx,nwl-pcie-2.11";
125            reg = <0x0 0xfd0e0000 0x0 0x1000>,
126                  <0x0 0xfd480000 0x0 0x1000>,
127                  <0x80 0x00000000 0x0 0x10000000>;
128            reg-names = "breg", "pcireg", "cfg";
129            ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
130                     <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
131            #address-cells = <3>;
132            #size-cells = <2>;
133            #interrupt-cells = <1>;
134            msi-controller;
135            device_type = "pci";
136            interrupt-parent = <&gic>;
137            interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
138                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
139                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
140            interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
141            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
142            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
143                            <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
144                            <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
145                            <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
146            msi-parent = <&nwl_pcie>;
147            phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
148            power-domains = <&zynqmp_firmware PD_PCIE>;
149            iommus = <&smmu 0x4d0>;
150            pcie_intc: legacy-interrupt-controller {
151                interrupt-controller;
152                #address-cells = <0>;
153                #interrupt-cells = <1>;
154            };
155        };
156    };