ti,j721e-pci-host.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: TI J721E PCI Host (PCIe Wrapper)
  9
 10maintainers:
 11  - Kishon Vijay Abraham I <kishon@ti.com>
 12
 13properties:
 14  compatible:
 15    oneOf:
 16      - const: ti,j721e-pcie-host
 17      - const: ti,j784s4-pcie-host
 18      - description: PCIe controller in AM64
 19        items:
 20          - const: ti,am64-pcie-host
 21          - const: ti,j721e-pcie-host
 22      - description: PCIe controller in J7200
 23        items:
 24          - const: ti,j7200-pcie-host
 25          - const: ti,j721e-pcie-host
 26      - description: PCIe controller in J722S
 27        items:
 28          - const: ti,j722s-pcie-host
 29          - const: ti,j721e-pcie-host
 30
 31  reg:
 32    maxItems: 4
 33
 34  reg-names:
 35    items:
 36      - const: intd_cfg
 37      - const: user_cfg
 38      - const: reg
 39      - const: cfg
 40
 41  ti,syscon-acspcie-proxy-ctrl:
 42    $ref: /schemas/types.yaml#/definitions/phandle-array
 43    items:
 44      - items:
 45          - description: Phandle to the ACSPCIE Proxy Control Register
 46          - description: Bitmask corresponding to the PAD IO Buffer
 47                         output enable fields (Active Low).
 48    description: Specifier for enabling the ACSPCIE PAD outputs to drive
 49                 the reference clock to the Endpoint device.
 50
 51  ti,syscon-pcie-ctrl:
 52    $ref: /schemas/types.yaml#/definitions/phandle-array
 53    items:
 54      - items:
 55          - description: Phandle to the SYSCON entry
 56          - description: pcie_ctrl register offset within SYSCON
 57    description: Specifier for configuring PCIe mode and link speed.
 58
 59  power-domains:
 60    maxItems: 1
 61
 62  clocks:
 63    minItems: 1
 64    maxItems: 2
 65    description: |+
 66      clock-specifier to represent input to the PCIe for 1 item.
 67      2nd item if present represents reference clock to the connector.
 68
 69  clock-names:
 70    minItems: 1
 71    items:
 72      - const: fck
 73      - const: pcie_refclk
 74
 75  dma-coherent: true
 76
 77  vendor-id:
 78    const: 0x104c
 79
 80  device-id:
 81    enum:
 82      - 0xb00d
 83      - 0xb00f
 84      - 0xb010
 85      - 0xb012
 86      - 0xb013
 87
 88  msi-map: true
 89
 90  interrupts:
 91    maxItems: 1
 92
 93  interrupt-names:
 94    items:
 95      - const: link_state
 96
 97  interrupt-controller:
 98    type: object
 99    additionalProperties: false
100
101    properties:
102      '#address-cells':
103        const: 0
104
105      interrupt-controller: true
106
107      '#interrupt-cells':
108        const: 1
109
110      interrupts:
111        maxItems: 1
112
113allOf:
114  - $ref: cdns-pcie-host.yaml#
115  - if:
116      properties:
117        compatible:
118          enum:
119            - ti,am64-pcie-host
120    then:
121      properties:
122        num-lanes:
123          const: 1
124
125  - if:
126      properties:
127        compatible:
128          enum:
129            - ti,j7200-pcie-host
130            - ti,j721e-pcie-host
131    then:
132      properties:
133        num-lanes:
134          minimum: 1
135          maximum: 2
136
137  - if:
138      properties:
139        compatible:
140          enum:
141            - ti,j784s4-pcie-host
142    then:
143      properties:
144        num-lanes:
145          minimum: 1
146          maximum: 4
147
148required:
149  - compatible
150  - reg
151  - reg-names
152  - ti,syscon-pcie-ctrl
153  - max-link-speed
154  - num-lanes
155  - power-domains
156  - clocks
157  - clock-names
158  - vendor-id
159  - device-id
160  - msi-map
161  - dma-ranges
162  - ranges
163  - reset-gpios
164  - phys
165  - phy-names
166
167unevaluatedProperties: false
168
169examples:
170  - |
171    #include <dt-bindings/soc/ti,sci_pm_domain.h>
172    #include <dt-bindings/gpio/gpio.h>
173
174    bus {
175        #address-cells = <2>;
176        #size-cells = <2>;
177
178        pcie0_rc: pcie@2900000 {
179            compatible = "ti,j721e-pcie-host";
180            reg = <0x00 0x02900000 0x00 0x1000>,
181                  <0x00 0x02907000 0x00 0x400>,
182                  <0x00 0x0d000000 0x00 0x00800000>,
183                  <0x00 0x10000000 0x00 0x00001000>;
184            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
185            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
186            max-link-speed = <3>;
187            num-lanes = <2>;
188            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
189            clocks = <&k3_clks 239 1>;
190            clock-names = "fck";
191            device_type = "pci";
192            #address-cells = <3>;
193            #size-cells = <2>;
194            bus-range = <0x0 0xf>;
195            vendor-id = <0x104c>;
196            device-id = <0xb00d>;
197            msi-map = <0x0 &gic_its 0x0 0x10000>;
198            dma-coherent;
199            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
200            phys = <&serdes0_pcie_link>;
201            phy-names = "pcie-phy";
202            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
203                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
204            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
205        };
206    };