ti,j721e-pci-ep.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: TI J721E PCI EP (PCIe Wrapper)
  9
 10maintainers:
 11  - Kishon Vijay Abraham I <kishon@ti.com>
 12
 13properties:
 14  compatible:
 15    oneOf:
 16      - const: ti,j721e-pcie-ep
 17      - const: ti,j784s4-pcie-ep
 18      - description: PCIe EP controller in AM64
 19        items:
 20          - const: ti,am64-pcie-ep
 21          - const: ti,j721e-pcie-ep
 22      - description: PCIe EP controller in J7200
 23        items:
 24          - const: ti,j7200-pcie-ep
 25          - const: ti,j721e-pcie-ep
 26
 27  reg:
 28    maxItems: 4
 29
 30  reg-names:
 31    items:
 32      - const: intd_cfg
 33      - const: user_cfg
 34      - const: reg
 35      - const: mem
 36
 37  ti,syscon-pcie-ctrl:
 38    $ref: /schemas/types.yaml#/definitions/phandle-array
 39    items:
 40      - items:
 41          - description: Phandle to the SYSCON entry
 42          - description: pcie_ctrl register offset within SYSCON
 43    description: Specifier for configuring PCIe mode and link speed.
 44
 45  power-domains:
 46    maxItems: 1
 47
 48  clocks:
 49    maxItems: 1
 50    description: clock-specifier to represent input to the PCIe
 51
 52  clock-names:
 53    items:
 54      - const: fck
 55
 56  dma-coherent:
 57    description: Indicates that the PCIe IP block can ensure the coherency
 58
 59  interrupts:
 60    maxItems: 1
 61
 62  interrupt-names:
 63    items:
 64      - const: link_state
 65
 66allOf:
 67  - $ref: cdns-pcie-ep.yaml#
 68  - if:
 69      properties:
 70        compatible:
 71          enum:
 72            - ti,am64-pcie-ep
 73    then:
 74      properties:
 75        num-lanes:
 76          const: 1
 77
 78  - if:
 79      properties:
 80        compatible:
 81          enum:
 82            - ti,j7200-pcie-ep
 83            - ti,j721e-pcie-ep
 84    then:
 85      properties:
 86        num-lanes:
 87          minimum: 1
 88          maximum: 2
 89
 90  - if:
 91      properties:
 92        compatible:
 93          enum:
 94            - ti,j784s4-pcie-ep
 95    then:
 96      properties:
 97        num-lanes:
 98          minimum: 1
 99          maximum: 4
100
101required:
102  - compatible
103  - reg
104  - reg-names
105  - ti,syscon-pcie-ctrl
106  - max-link-speed
107  - num-lanes
108  - power-domains
109  - clocks
110  - clock-names
111  - max-functions
112  - phys
113  - phy-names
114
115unevaluatedProperties: false
116
117examples:
118  - |
119    #include <dt-bindings/soc/ti,sci_pm_domain.h>
120
121    bus {
122        #address-cells = <2>;
123        #size-cells = <2>;
124
125        pcie0_ep: pcie-ep@d000000 {
126            compatible = "ti,j721e-pcie-ep";
127            reg = <0x00 0x02900000 0x00 0x1000>,
128                  <0x00 0x02907000 0x00 0x400>,
129                  <0x00 0x0d000000 0x00 0x00800000>,
130                  <0x00 0x10000000 0x00 0x08000000>;
131            reg-names = "intd_cfg", "user_cfg", "reg", "mem";
132            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
133            max-link-speed = <3>;
134            num-lanes = <2>;
135            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
136            clocks = <&k3_clks 239 1>;
137            clock-names = "fck";
138            max-functions = /bits/ 8 <6>;
139            dma-coherent;
140            phys = <&serdes0_pcie_link>;
141            phy-names = "pcie-phy";
142        };
143    };