ti,am65-pci-host.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: TI AM65 PCI Host
  9
 10maintainers:
 11  - Kishon Vijay Abraham I <kishon@ti.com>
 12
 13allOf:
 14  - $ref: /schemas/pci/pci-host-bridge.yaml#
 15
 16properties:
 17  compatible:
 18    enum:
 19      - ti,am654-pcie-rc
 20      - ti,keystone-pcie
 21
 22  reg:
 23    minItems: 4
 24    maxItems: 6
 25
 26  reg-names:
 27    minItems: 4
 28    items:
 29      - const: app
 30      - const: dbics
 31      - const: config
 32      - const: atu
 33      - const: vmap_lp
 34      - const: vmap_hp
 35
 36  interrupts:
 37    maxItems: 1
 38
 39  power-domains:
 40    maxItems: 1
 41
 42  ti,syscon-pcie-id:
 43    $ref: /schemas/types.yaml#/definitions/phandle-array
 44    items:
 45      - items:
 46          - description: Phandle to the SYSCON entry
 47          - description: pcie_device_id register offset within SYSCON
 48    description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
 49
 50  ti,syscon-pcie-mode:
 51    $ref: /schemas/types.yaml#/definitions/phandle-array
 52    items:
 53      - items:
 54          - description: Phandle to the SYSCON entry
 55          - description: pcie_ctrl register offset within SYSCON
 56    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
 57
 58  msi-map: true
 59
 60  dma-coherent: true
 61
 62  num-viewport:
 63    $ref: /schemas/types.yaml#/definitions/uint32
 64
 65  phys:
 66    description: per-lane PHYs
 67    minItems: 1
 68    maxItems: 2
 69
 70  phy-names:
 71    minItems: 1
 72    maxItems: 2
 73    items:
 74      pattern: '^pcie-phy[0-1]$'
 75
 76  memory-region:
 77    maxItems: 1
 78    description: |
 79      phandle to a restricted DMA pool to be used for all devices behind
 80      this controller. The regions should be defined according to
 81      reserved-memory/shared-dma-pool.yaml.
 82      Note that enforcement via the PVU will only be available to
 83      ti,am654-pcie-rc devices.
 84
 85required:
 86  - compatible
 87  - reg
 88  - reg-names
 89  - max-link-speed
 90  - ti,syscon-pcie-id
 91  - ti,syscon-pcie-mode
 92  - ranges
 93
 94if:
 95  properties:
 96    compatible:
 97      enum:
 98        - ti,am654-pcie-rc
 99then:
100  required:
101    - dma-coherent
102    - power-domains
103    - msi-map
104    - num-viewport
105else:
106  properties:
107    reg:
108      maxItems: 4
109
110    reg-names:
111      maxItems: 4
112
113unevaluatedProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    #include <dt-bindings/interrupt-controller/irq.h>
119    #include <dt-bindings/phy/phy.h>
120    #include <dt-bindings/soc/ti,sci_pm_domain.h>
121
122    pcie0_rc: pcie@5500000 {
123        compatible = "ti,am654-pcie-rc";
124        reg =  <0x5500000 0x1000>,
125               <0x5501000 0x1000>,
126               <0x10000000 0x2000>,
127               <0x5506000 0x1000>,
128               <0x2900000 0x1000>,
129               <0x2908000 0x1000>;
130        reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp";
131        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
132        #address-cells = <3>;
133        #size-cells = <2>;
134        ranges = <0x81000000 0 0          0x10020000 0 0x00010000>,
135                 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
136        ti,syscon-pcie-id = <&scm_conf 0x0210>;
137        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
138        bus-range = <0x0 0xff>;
139        num-viewport = <16>;
140        max-link-speed = <2>;
141        dma-coherent;
142        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
143        msi-map = <0x0 &gic_its 0x0 0x10000>;
144        device_type = "pci";
145        num-lanes = <1>;
146        phys = <&serdes0 PHY_TYPE_PCIE 0>;
147        phy-names = "pcie-phy0";
148    };