starfive,jh7110-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: StarFive JH7110 PCIe host controller
  8
  9maintainers:
 10  - Kevin Xie <kevin.xie@starfivetech.com>
 11
 12allOf:
 13  - $ref: plda,xpressrich3-axi-common.yaml#
 14
 15properties:
 16  compatible:
 17    const: starfive,jh7110-pcie
 18
 19  reg:
 20    maxItems: 2
 21
 22  reg-names:
 23    maxItems: 2
 24
 25  clocks:
 26    items:
 27      - description: NOC bus clock
 28      - description: Transport layer clock
 29      - description: AXI MST0 clock
 30      - description: APB clock
 31
 32  clock-names:
 33    items:
 34      - const: noc
 35      - const: tl
 36      - const: axi_mst0
 37      - const: apb
 38
 39  resets:
 40    items:
 41      - description: AXI MST0 reset
 42      - description: AXI SLAVE0 reset
 43      - description: AXI SLAVE reset
 44      - description: PCIE BRIDGE reset
 45      - description: PCIE CORE reset
 46      - description: PCIE APB reset
 47
 48  reset-names:
 49    items:
 50      - const: mst0
 51      - const: slv0
 52      - const: slv
 53      - const: brg
 54      - const: core
 55      - const: apb
 56
 57  starfive,stg-syscon:
 58    $ref: /schemas/types.yaml#/definitions/phandle-array
 59    description:
 60      The phandle to System Register Controller syscon node.
 61
 62  perst-gpios:
 63    description: GPIO controlled connection to PERST# signal
 64    maxItems: 1
 65
 66  phys:
 67    description:
 68      Specified PHY is attached to PCIe controller.
 69    maxItems: 1
 70
 71required:
 72  - clocks
 73  - resets
 74  - starfive,stg-syscon
 75
 76unevaluatedProperties: false
 77
 78examples:
 79  - |
 80    #include <dt-bindings/gpio/gpio.h>
 81    soc {
 82        #address-cells = <2>;
 83        #size-cells = <2>;
 84
 85        pcie@940000000 {
 86            compatible = "starfive,jh7110-pcie";
 87            reg = <0x9 0x40000000 0x0 0x10000000>,
 88                  <0x0 0x2b000000 0x0 0x1000000>;
 89            reg-names = "cfg", "apb";
 90            #address-cells = <3>;
 91            #size-cells = <2>;
 92            #interrupt-cells = <1>;
 93            device_type = "pci";
 94            ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
 95                     <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 96            starfive,stg-syscon = <&stg_syscon>;
 97            bus-range = <0x0 0xff>;
 98            interrupt-parent = <&plic>;
 99            interrupts = <56>;
100            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
101            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
102                            <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
103                            <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
104                            <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
105            msi-controller;
106            clocks = <&syscrg 86>,
107                     <&stgcrg 10>,
108                     <&stgcrg 8>,
109                     <&stgcrg 9>;
110            clock-names = "noc", "tl", "axi_mst0", "apb";
111            resets = <&stgcrg 11>,
112                     <&stgcrg 12>,
113                     <&stgcrg 13>,
114                     <&stgcrg 14>,
115                     <&stgcrg 15>,
116                     <&stgcrg 16>;
117            perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
118            phys = <&pciephy0>;
119
120            pcie_intc0: interrupt-controller {
121                #address-cells = <0>;
122                #interrupt-cells = <1>;
123                interrupt-controller;
124            };
125        };
126    };