spacemit,k1-pcie-host.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: SpacemiT K1 PCI Express Host Controller
  8
  9maintainers:
 10  - Alex Elder <elder@riscstar.com>
 11
 12description: >
 13  The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare
 14  PCIe IP.  The controller uses the DesignWare built-in MSI interrupt
 15  controller, and supports 256 MSIs.
 16
 17allOf:
 18  - $ref: /schemas/pci/snps,dw-pcie.yaml#
 19
 20properties:
 21  compatible:
 22    const: spacemit,k1-pcie
 23
 24  reg:
 25    items:
 26      - description: DesignWare PCIe registers
 27      - description: ATU address space
 28      - description: PCIe configuration space
 29      - description: Link control registers
 30
 31  reg-names:
 32    items:
 33      - const: dbi
 34      - const: atu
 35      - const: config
 36      - const: link
 37
 38  clocks:
 39    items:
 40      - description: DWC PCIe Data Bus Interface (DBI) clock
 41      - description: DWC PCIe application AXI-bus master interface clock
 42      - description: DWC PCIe application AXI-bus slave interface clock
 43
 44  clock-names:
 45    items:
 46      - const: dbi
 47      - const: mstr
 48      - const: slv
 49
 50  resets:
 51    items:
 52      - description: DWC PCIe Data Bus Interface (DBI) reset
 53      - description: DWC PCIe application AXI-bus master interface reset
 54      - description: DWC PCIe application AXI-bus slave interface reset
 55
 56  reset-names:
 57    items:
 58      - const: dbi
 59      - const: mstr
 60      - const: slv
 61
 62  interrupts:
 63    items:
 64      - description: Interrupt used for MSIs
 65
 66  interrupt-names:
 67    const: msi
 68
 69  spacemit,apmu:
 70    $ref: /schemas/types.yaml#/definitions/phandle-array
 71    description:
 72      A phandle that refers to the APMU system controller, whose regmap is
 73      used in managing resets and link state, along with and offset of its
 74      reset control register.
 75    items:
 76      - items:
 77          - description: phandle to APMU system controller
 78          - description: register offset
 79
 80patternProperties:
 81  '^pcie@':
 82    type: object
 83    $ref: /schemas/pci/pci-pci-bridge.yaml#
 84
 85    properties:
 86      phys:
 87        maxItems: 1
 88
 89      vpcie3v3-supply:
 90        description:
 91          A phandle for 3.3v regulator to use for PCIe
 92
 93    required:
 94      - phys
 95      - vpcie3v3-supply
 96
 97    unevaluatedProperties: false
 98
 99required:
100  - clocks
101  - clock-names
102  - resets
103  - reset-names
104  - interrupts
105  - interrupt-names
106  - spacemit,apmu
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    #include <dt-bindings/clock/spacemit,k1-syscon.h>
113    pcie@ca400000 {
114        device_type = "pci";
115        compatible = "spacemit,k1-pcie";
116        reg = <0xca400000 0x00001000>,
117              <0xca700000 0x0001ff24>,
118              <0x9f000000 0x00002000>,
119              <0xc0c20000 0x00001000>;
120        reg-names = "dbi",
121                    "atu",
122                    "config",
123                    "link";
124        #address-cells = <3>;
125        #size-cells = <2>;
126        ranges = <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>,
127                 <0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>;
128        interrupts = <142>;
129        interrupt-names = "msi";
130        clocks = <&syscon_apmu CLK_PCIE1_DBI>,
131                 <&syscon_apmu CLK_PCIE1_MASTER>,
132                 <&syscon_apmu CLK_PCIE1_SLAVE>;
133        clock-names = "dbi",
134                      "mstr",
135                      "slv";
136        resets = <&syscon_apmu RESET_PCIE1_DBI>,
137                 <&syscon_apmu RESET_PCIE1_MASTER>,
138                 <&syscon_apmu RESET_PCIE1_SLAVE>;
139        reset-names = "dbi",
140                      "mstr",
141                      "slv";
142        pinctrl-names = "default";
143        pinctrl-0 = <&pcie1_3_cfg>;
144        spacemit,apmu = <&syscon_apmu 0x3d4>;
145
146        pcie@0 {
147          device_type = "pci";
148          compatible = "pciclass,0604";
149          reg = <0x0 0x0 0x0 0x0 0x0>;
150          bus-range = <0x01 0xff>;
151          #address-cells = <3>;
152          #size-cells = <2>;
153          ranges;
154          phys = <&pcie1_phy>;
155          vpcie3v3-supply = <&pcie_vcc_3v3>;
156        };
157    };