sophgo,sg2042-pcie-host.yaml

 1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
 8
 9description:
10  Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
11
12maintainers:
13  - Chen Wang <unicorn_wang@outlook.com>
14
15properties:
16  compatible:
17    const: sophgo,sg2042-pcie-host
18
19  reg:
20    maxItems: 2
21
22  reg-names:
23    items:
24      - const: reg
25      - const: cfg
26
27  vendor-id:
28    const: 0x1f1c
29
30  device-id:
31    const: 0x2042
32
33  msi-parent: true
34
35allOf:
36  - $ref: cdns-pcie-host.yaml#
37
38required:
39  - compatible
40  - reg
41  - reg-names
42
43unevaluatedProperties: false
44
45examples:
46  - |
47    #include <dt-bindings/interrupt-controller/irq.h>
48
49    pcie@62000000 {
50      compatible = "sophgo,sg2042-pcie-host";
51      device_type = "pci";
52      reg = <0x62000000  0x00800000>,
53            <0x48000000  0x00001000>;
54      reg-names = "reg", "cfg";
55      #address-cells = <3>;
56      #size-cells = <2>;
57      ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
58               <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
59      bus-range = <0x00 0xff>;
60      vendor-id = <0x1f1c>;
61      device-id = <0x2042>;
62      cdns,no-bar-match-nbits = <48>;
63      msi-parent = <&msi>;
64    };