socionext,uniphier-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Socionext UniPhier PCIe host controller
  8
  9description: |
 10  UniPhier PCIe host controller is based on the Synopsys DesignWare
 11  PCI core. It shares common features with the PCIe DesignWare core and
 12  inherits common properties defined in
 13  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 14
 15maintainers:
 16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
 17
 18allOf:
 19  - $ref: /schemas/pci/snps,dw-pcie.yaml#
 20
 21properties:
 22  compatible:
 23    enum:
 24      - socionext,uniphier-pcie
 25
 26  reg:
 27    minItems: 3
 28    maxItems: 4
 29
 30  reg-names:
 31    minItems: 3
 32    items:
 33      - const: dbi
 34      - const: link
 35      - const: config
 36      - const: atu
 37
 38  clocks:
 39    maxItems: 1
 40
 41  resets:
 42    maxItems: 1
 43
 44  num-viewport: true
 45
 46  num-lanes: true
 47
 48  phys:
 49    maxItems: 1
 50
 51  phy-names:
 52    const: pcie-phy
 53
 54  interrupt-controller:
 55    type: object
 56    additionalProperties: false
 57
 58    properties:
 59      '#address-cells':
 60        const: 0
 61
 62      interrupt-controller: true
 63
 64      '#interrupt-cells':
 65        const: 1
 66
 67      interrupts:
 68        maxItems: 1
 69
 70required:
 71  - compatible
 72  - reg
 73  - reg-names
 74  - clocks
 75  - resets
 76
 77unevaluatedProperties: false
 78
 79examples:
 80  - |
 81    bus {
 82        gic: interrupt-controller {
 83            interrupt-controller;
 84            #interrupt-cells = <3>;
 85        };
 86    };
 87
 88    pcie: pcie@66000000 {
 89        compatible = "socionext,uniphier-pcie";
 90        reg-names = "dbi", "link", "config";
 91        reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
 92        #address-cells = <3>;
 93        #size-cells = <2>;
 94        clocks = <&sys_clk 24>;
 95        resets = <&sys_rst 24>;
 96        num-lanes = <1>;
 97        num-viewport = <1>;
 98        bus-range = <0x0 0xff>;
 99        device_type = "pci";
100        ranges = <0x81000000 0 0x00000000  0x2ffe0000  0 0x00010000>,
101                 <0x82000000 0 0x00000000  0x20000000  0 0x0ffe0000>;
102        phy-names = "pcie-phy";
103        phys = <&pcie_phy>;
104        #interrupt-cells = <1>;
105        interrupt-names = "dma", "msi";
106        interrupt-parent = <&gic>;
107        interrupts = <0 224 4>, <0 225 4>;
108        interrupt-map-mask = <0 0 0  7>;
109        interrupt-map = <0 0 0  1  &pcie_intc 0>,
110                        <0 0 0  2  &pcie_intc 1>,
111                        <0 0 0  3  &pcie_intc 2>,
112                        <0 0 0  4  &pcie_intc 3>;
113
114        pcie_intc: interrupt-controller {
115            #address-cells = <0>;
116            interrupt-controller;
117            #interrupt-cells = <1>;
118            interrupt-parent = <&gic>;
119            interrupts = <0 226 4>;
120        };
121    };