snps,dw-pcie.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Synopsys DesignWare PCIe interface
  8
  9maintainers:
 10  - Jingoo Han <jingoohan1@gmail.com>
 11  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
 12
 13description: |
 14  Synopsys DesignWare PCIe host controller
 15
 16# Please create a separate DT-schema for your DWC PCIe Root Port controller
 17# and make sure it's assigned with the vendor-specific compatible string.
 18select:
 19  properties:
 20    compatible:
 21      const: snps,dw-pcie
 22  required:
 23    - compatible
 24
 25allOf:
 26  - $ref: /schemas/pci/pci-host-bridge.yaml#
 27  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
 28  - if:
 29      not:
 30        required:
 31          - msi-map
 32    then:
 33      properties:
 34        interrupt-names:
 35          contains:
 36            const: msi
 37
 38properties:
 39  reg:
 40    description:
 41      At least DBI reg-space and peripheral devices CFG-space outbound window
 42      are required for the normal controller work. iATU memory IO region is
 43      also required if the space is unrolled (IP-core version >= 4.80a).
 44    minItems: 2
 45    maxItems: 7
 46
 47  reg-names:
 48    minItems: 2
 49    maxItems: 7
 50    items:
 51      oneOf:
 52        - description:
 53            Basic DWC PCIe controller configuration-space accessible over
 54            the DBI interface. This memory space is either activated with
 55            CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
 56            with all spaces. Note iATU/eDMA CSRs are indirectly accessible
 57            via the PL viewports on the DWC PCIe controllers older than
 58            v4.80a.
 59          const: dbi
 60        - description:
 61            Shadow DWC PCIe config-space registers. This space is selected
 62            by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
 63            the PCI-SIG PCIe CFG-space with the shadow registers for some
 64            PCI Header space, PCI Standard and Extended Structures. It's
 65            mainly relevant for the end-point controller configuration,
 66            but still there are some shadow registers available for the
 67            Root Port mode too.
 68          const: dbi2
 69        - description:
 70            External Local Bus registers. It's an application-dependent
 71            registers normally defined by the platform engineers. The space
 72            can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
 73            be accessed over some platform-specific means (for instance
 74            as a part of a system controller).
 75          enum: [ elbi, app ]
 76        - description:
 77            iATU/eDMA registers common for all device functions. It's an
 78            unrolled memory space with the internal Address Translation
 79            Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
 80            and CS2 = 1. For IP-core releases prior v4.80a, these registers
 81            have been programmed via an indirect addressing scheme using a
 82            set of viewport CSRs mapped into the PL space. Note iATU is
 83            normally mapped to the 0x0 address of this region, while eDMA
 84            is available at 0x80000 base address.
 85          const: atu
 86        - description:
 87            Platform-specific eDMA registers. Some platforms may have eDMA
 88            CSRs mapped in a non-standard base address. The registers offset
 89            can be changed or the MS/LS-bits of the address can be attached
 90            in an additional RTL block before the MEM-IO transactions reach
 91            the DW PCIe slave interface.
 92          const: dma
 93        - description:
 94            PHY/PCS configuration registers. Some platforms can have the
 95            PCS and PHY CSRs accessible over a dedicated memory mapped
 96            region, but mainly these registers are indirectly accessible
 97            either by means of the embedded PHY viewport schema or by some
 98            platform-specific method.
 99          const: phy
100        - description:
101            Outbound iATU-capable memory-region which will be used to access
102            the peripheral PCIe devices configuration space.
103          const: config
104        - description:
105            Vendor-specific CSR names. Consider using the generic names above
106            for new bindings.
107          oneOf:
108            - description: See native 'dbi' CSR region for details.
109              enum: [ ctrl ]
110            - description: See native 'elbi/app' CSR region for details.
111              enum: [ apb, mgmt, link, ulreg, appl, controller ]
112            - description: See native 'atu' CSR region for details.
113              enum: [ atu_dma ]
114            - description: Syscon-related CSR regions.
115              enum: [ smu, mpu ]
116            - description: Tegra234 aperture
117              enum: [ ecam ]
118            - description: AMD MDB PCIe SLCR region
119              const: slcr
120    allOf:
121      - contains:
122          enum: [ dbi, ctrl ]
123      - contains:
124          const: config
125
126  interrupts:
127    description:
128      DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
129      signal is supposed to be specified for the host controller.
130    minItems: 1
131    maxItems: 26
132
133  interrupt-names:
134    minItems: 1
135    maxItems: 26
136    items:
137      oneOf:
138        - description:
139            Controller request to read or write virtual product data
140            from/to the VPD capability registers.
141          const: vpd
142        - description:
143            Link Equalization Request flag is set in the Link Status 2
144            register (applicable if the corresponding IRQ is enabled in
145            the Link Control 3 register).
146          const: l_eq
147        - description:
148            Indicates that the eDMA Tx/Rx transfer is complete or that an
149            error has occurred on the corresponding channel. eDMA can have
150            eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
151            to 16 IRQ signals all together. Write eDMA channels shall go
152            first in the ordered row as per default edma_int[*] bus setup.
153          pattern: '^dma([0-9]|1[0-5])?$'
154        - description:
155            PCIe protocol correctable error or a Data Path protection
156            correctable error is detected by the automotive/safety
157            feature.
158          const: sft_ce
159        - description:
160            Indicates that the internal safety mechanism has detected an
161            uncorrectable error.
162          const: sft_ue
163        - description:
164            Application-specific IRQ raised depending on the vendor-specific
165            events basis.
166          const: app
167        - description:
168            DSP AXI MSI Interrupt detected. It gets de-asserted when there is
169            no more MSI interrupt pending. The interrupt is relevant to the
170            iMSI-RX - Integrated MSI Receiver (AXI bridge).
171          const: msi
172        - description:
173            Legacy A/B/C/D interrupt signal. Basically it's triggered by
174            receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message
175            from the downstream device.
176          pattern: "^int(a|b|c|d)$"
177        - description:
178            Error condition detected and a flag is set in the Root Error Status
179            register of the AER capability. It's asserted when the RC
180            internally generated an error or an error message is received by
181            the RC.
182          const: aer
183        - description:
184            PME message is received by the port. That means having the PME
185            status bit set in the Root Status register (the event is
186            supposed to be unmasked in the Root Control register).
187          const: pme
188        - description:
189            Hot-plug event is detected. That is a bit has been set in the
190            Slot Status register and the corresponding event is enabled in
191            the Slot Control register.
192          const: hp
193        - description:
194            Link Autonomous Bandwidth Status flag has been set in the Link
195            Status register (the event is supposed to be unmasked in the
196            Link Control register).
197          const: bw_au
198        - description:
199            Bandwidth Management Status flag has been set in the Link
200            Status register (the event is supposed to be unmasked in the
201            Link Control register).
202          const: bw_mg
203        - description:
204            Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for
205            details.
206          const: legacy
207        - description:
208            Vendor-specific IRQ names. Consider using the generic names above
209            for new bindings.
210          oneOf:
211            - description: See native "app" IRQ for details
212              enum: [ intr, sys, pmc, msg, err ]
213
214additionalProperties: true
215
216required:
217  - compatible
218  - reg
219  - reg-names
220
221examples:
222  - |
223    pcie@dfc00000 {
224      compatible = "snps,dw-pcie";
225      device_type = "pci";
226      reg = <0xdfc00000 0x0001000>, /* IP registers */
227            <0xd0000000 0x0002000>; /* Configuration space */
228      reg-names = "dbi", "config";
229      #address-cells = <3>;
230      #size-cells = <2>;
231      ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
232               <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
233      bus-range = <0x0 0xff>;
234
235      interrupts = <25>, <24>;
236      interrupt-names = "msi", "hp";
237
238      reset-gpios = <&port0 0 1>;
239
240      phys = <&pcie_phy>;
241      phy-names = "pcie";
242
243      num-lanes = <1>;
244      max-link-speed = <3>;
245    };