rockchip-dw-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
  8
  9maintainers:
 10  - Shawn Lin <shawn.lin@rock-chips.com>
 11  - Simon Xue <xxm@rock-chips.com>
 12  - Heiko Stuebner <heiko@sntech.de>
 13
 14description: |+
 15  RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
 16  PCIe IP and thus inherits all the common properties defined in
 17  snps,dw-pcie.yaml.
 18
 19properties:
 20  compatible:
 21    oneOf:
 22      - const: rockchip,rk3568-pcie
 23      - items:
 24          - enum:
 25              - rockchip,rk3528-pcie
 26              - rockchip,rk3562-pcie
 27              - rockchip,rk3576-pcie
 28              - rockchip,rk3588-pcie
 29          - const: rockchip,rk3568-pcie
 30
 31  reg:
 32    items:
 33      - description: Data Bus Interface (DBI) registers
 34      - description: Rockchip designed configuration registers
 35      - description: Config registers
 36
 37  reg-names:
 38    items:
 39      - const: dbi
 40      - const: apb
 41      - const: config
 42
 43  legacy-interrupt-controller:
 44    description: Interrupt controller node for handling legacy PCI interrupts.
 45    type: object
 46    additionalProperties: false
 47    properties:
 48      "#address-cells":
 49        const: 0
 50
 51      "#interrupt-cells":
 52        const: 1
 53
 54      interrupt-controller: true
 55
 56      interrupts:
 57        items:
 58          - description: combined legacy interrupt
 59    required:
 60      - "#address-cells"
 61      - "#interrupt-cells"
 62      - interrupt-controller
 63      - interrupts
 64
 65  msi-map: true
 66
 67  ranges:
 68    minItems: 2
 69    maxItems: 3
 70
 71  vpcie3v3-supply: true
 72
 73allOf:
 74  - $ref: /schemas/pci/snps,dw-pcie.yaml#
 75  - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
 76  - if:
 77      not:
 78        properties:
 79          compatible:
 80            contains:
 81              enum:
 82                - rockchip,rk3528-pcie
 83                - rockchip,rk3562-pcie
 84                - rockchip,rk3576-pcie
 85    then:
 86      required:
 87        - msi-map
 88
 89  - if:
 90      properties:
 91        compatible:
 92          contains:
 93            enum:
 94              - rockchip,rk3528-pcie
 95              - rockchip,rk3562-pcie
 96              - rockchip,rk3576-pcie
 97    then:
 98      properties:
 99        interrupts:
100          minItems: 6
101          maxItems: 6
102        interrupt-names:
103          items:
104            - const: sys
105            - const: pmc
106            - const: msg
107            - const: legacy
108            - const: err
109            - const: msi
110    else:
111      properties:
112        interrupts:
113          minItems: 5
114        interrupt-names:
115          minItems: 5
116          items:
117            - const: sys
118            - const: pmc
119            - const: msg
120            - const: legacy
121            - const: err
122            - const: dma0
123            - const: dma1
124            - const: dma2
125            - const: dma3
126
127unevaluatedProperties: false
128
129examples:
130  - |
131    #include <dt-bindings/interrupt-controller/arm-gic.h>
132
133    bus {
134        #address-cells = <2>;
135        #size-cells = <2>;
136
137        pcie3x2: pcie@fe280000 {
138            compatible = "rockchip,rk3568-pcie";
139            reg = <0x3 0xc0800000 0x0 0x390000>,
140                  <0x0 0xfe280000 0x0 0x10000>,
141                  <0x3 0x80000000 0x0 0x100000>;
142            reg-names = "dbi", "apb", "config";
143            bus-range = <0x20 0x2f>;
144            clocks = <&cru 143>, <&cru 144>,
145                     <&cru 145>, <&cru 146>,
146                     <&cru 147>;
147            clock-names = "aclk_mst", "aclk_slv",
148                          "aclk_dbi", "pclk",
149                          "aux";
150            device_type = "pci";
151            interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
152                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
153                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
154                         <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
155                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
156            interrupt-names = "sys", "pmc", "msg", "legacy", "err";
157            linux,pci-domain = <2>;
158            max-link-speed = <2>;
159            msi-map = <0x2000 &its 0x2000 0x1000>;
160            num-lanes = <2>;
161            phys = <&pcie30phy>;
162            phy-names = "pcie-phy";
163            power-domains = <&power 15>;
164            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
165                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
166            resets = <&cru 193>;
167            reset-names = "pipe";
168            #address-cells = <3>;
169            #size-cells = <2>;
170
171            legacy-interrupt-controller {
172                interrupt-controller;
173                #address-cells = <0>;
174                #interrupt-cells = <1>;
175                interrupt-parent = <&gic>;
176                interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
177            };
178        };
179    };
180...