rockchip-dw-pcie-common.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
  8
  9maintainers:
 10  - Shawn Lin <shawn.lin@rock-chips.com>
 11  - Simon Xue <xxm@rock-chips.com>
 12  - Heiko Stuebner <heiko@sntech.de>
 13
 14description: |+
 15  Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
 16  SoCs.
 17
 18properties:
 19  clocks:
 20    minItems: 5
 21    items:
 22      - description: AHB clock for PCIe master
 23      - description: AHB clock for PCIe slave
 24      - description: AHB clock for PCIe dbi
 25      - description: APB clock for PCIe
 26      - description: Auxiliary clock for PCIe
 27      - description: PIPE clock
 28      - description: Reference clock for PCIe
 29
 30  clock-names:
 31    minItems: 5
 32    items:
 33      - const: aclk_mst
 34      - const: aclk_slv
 35      - const: aclk_dbi
 36      - const: pclk
 37      - const: aux
 38      - const: pipe
 39      - const: ref
 40
 41  interrupts:
 42    minItems: 5
 43    items:
 44      - description:
 45          Combined system interrupt, which is used to signal the following
 46          interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
 47          hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
 48          edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
 49      - description:
 50          Combined PM interrupt, which is used to signal the following
 51          interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
 52          linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
 53          linkst_out_l0s, pm_dstate_update
 54      - description:
 55          Combined message interrupt, which is used to signal the following
 56          interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
 57          pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
 58      - description:
 59          Combined legacy interrupt, which is used to signal the following
 60          interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
 61          tx_intd
 62      - description:
 63          Combined error interrupt, which is used to signal the following
 64          interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
 65          tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
 66          nf_err_rx, f_err_rx, radm_qoverflow
 67      - description:
 68          If the matching interrupt name is "msi", then this is the combined
 69          MSI line interrupt, which is to support MSI interrupts output to GIC
 70          controller via GIC SPI interrupt instead of GIC ITS interrupt.
 71          If the matching interrupt name is "dma0", then this is the eDMA write
 72          channel 0 interrupt.
 73      - description:
 74          eDMA write channel 1 interrupt
 75      - description:
 76          eDMA read channel 0 interrupt
 77      - description:
 78          eDMA read channel 1 interrupt
 79
 80  interrupt-names:
 81    minItems: 5
 82    items:
 83      - const: sys
 84      - const: pmc
 85      - const: msg
 86      - const: legacy
 87      - const: err
 88      - enum:
 89          - msi
 90          - dma0
 91      - const: dma1
 92      - const: dma2
 93      - const: dma3
 94
 95  num-lanes: true
 96
 97  phys:
 98    maxItems: 1
 99
100  phy-names:
101    const: pcie-phy
102
103  power-domains:
104    maxItems: 1
105
106  resets:
107    minItems: 1
108    maxItems: 2
109
110  reset-names:
111    oneOf:
112      - const: pipe
113      - items:
114          - const: pwr
115          - const: pipe
116
117required:
118  - compatible
119  - reg
120  - reg-names
121  - clocks
122  - clock-names
123  - num-lanes
124  - phys
125  - phy-names
126  - power-domains
127  - resets
128  - reset-names
129
130additionalProperties: true
131
132...