qcom,pcie-x1e80100.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm X1E80100 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
 15  the Synopsys DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    const: qcom,pcie-x1e80100
 20
 21  reg:
 22    minItems: 6
 23    maxItems: 6
 24
 25  reg-names:
 26    items:
 27      - const: parf # Qualcomm specific registers
 28      - const: dbi # DesignWare PCIe registers
 29      - const: elbi # External local bus interface registers
 30      - const: atu # ATU address space
 31      - const: config # PCIe configuration space
 32      - const: mhi # MHI registers
 33
 34  clocks:
 35    minItems: 6
 36    maxItems: 7
 37
 38  clock-names:
 39    minItems: 6
 40    items:
 41      - const: aux # Auxiliary clock
 42      - const: cfg # Configuration clock
 43      - const: bus_master # Master AXI clock
 44      - const: bus_slave # Slave AXI clock
 45      - const: slave_q2a # Slave Q2A clock
 46      - const: noc_aggr # Aggre NoC PCIe AXI clock
 47      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
 48
 49  interrupts:
 50    minItems: 8
 51    maxItems: 9
 52
 53  interrupt-names:
 54    minItems: 8
 55    items:
 56      - const: msi0
 57      - const: msi1
 58      - const: msi2
 59      - const: msi3
 60      - const: msi4
 61      - const: msi5
 62      - const: msi6
 63      - const: msi7
 64      - const: global
 65
 66  resets:
 67    minItems: 1
 68    maxItems: 2
 69
 70  reset-names:
 71    minItems: 1
 72    items:
 73      - const: pci # PCIe core reset
 74      - const: link_down # PCIe link down reset
 75
 76required:
 77  - power-domains
 78  - resets
 79  - reset-names
 80
 81allOf:
 82  - $ref: qcom,pcie-common.yaml#
 83
 84unevaluatedProperties: false
 85
 86examples:
 87  - |
 88    #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
 89    #include <dt-bindings/gpio/gpio.h>
 90    #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
 91    #include <dt-bindings/interrupt-controller/arm-gic.h>
 92
 93    soc {
 94        #address-cells = <2>;
 95        #size-cells = <2>;
 96
 97        pcie@1c08000 {
 98            compatible = "qcom,pcie-x1e80100";
 99            reg = <0 0x01c08000 0 0x3000>,
100                  <0 0x7c000000 0 0xf1d>,
101                  <0 0x7c000f40 0 0xa8>,
102                  <0 0x7c001000 0 0x1000>,
103                  <0 0x7c100000 0 0x100000>,
104                  <0 0x01c0b000 0 0x1000>;
105            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
106            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
107                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
108
109            bus-range = <0x00 0xff>;
110            device_type = "pci";
111            linux,pci-domain = <0>;
112            num-lanes = <2>;
113
114            #address-cells = <3>;
115            #size-cells = <2>;
116
117            clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
118                     <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
119                     <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
120                     <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
121                     <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
122                     <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
123                     <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
124            clock-names = "aux",
125                          "cfg",
126                          "bus_master",
127                          "bus_slave",
128                          "slave_q2a",
129                          "noc_aggr",
130                          "cnoc_sf_axi";
131
132            dma-coherent;
133
134            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
135                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
143            interrupt-names = "msi0", "msi1", "msi2", "msi3",
144                              "msi4", "msi5", "msi6", "msi7", "global";
145            #interrupt-cells = <1>;
146            interrupt-map-mask = <0 0 0 0x7>;
147            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
148                            <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
149                            <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
150                            <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
151
152            interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
153                            <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
154            interconnect-names = "pcie-mem", "cpu-pcie";
155
156            iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
157                        <0x100 &apps_smmu 0x1401 0x1>;
158
159            phys = <&pcie4_phy>;
160            phy-names = "pciephy";
161
162            pinctrl-0 = <&pcie0_default_state>;
163            pinctrl-names = "default";
164
165            power-domains = <&gcc GCC_PCIE_4_GDSC>;
166
167            resets = <&gcc GCC_PCIE_4_BCR>;
168            reset-names = "pci";
169
170            perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
171            wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
172        };
173    };