qcom,pcie-sm8550.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8550 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
 15  the Synopsys DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - const: qcom,pcie-sm8550
 21      - items:
 22          - enum:
 23              - qcom,kaanapali-pcie
 24              - qcom,sar2130p-pcie
 25              - qcom,pcie-sm8650
 26              - qcom,pcie-sm8750
 27          - const: qcom,pcie-sm8550
 28
 29  reg:
 30    minItems: 5
 31    maxItems: 6
 32
 33  reg-names:
 34    minItems: 5
 35    items:
 36      - const: parf # Qualcomm specific registers
 37      - const: dbi # DesignWare PCIe registers
 38      - const: elbi # External local bus interface registers
 39      - const: atu # ATU address space
 40      - const: config # PCIe configuration space
 41      - const: mhi # MHI registers
 42
 43  clocks:
 44    minItems: 7
 45    maxItems: 9
 46
 47  clock-names:
 48    minItems: 7
 49    items:
 50      - const: aux # Auxiliary clock
 51      - const: cfg # Configuration clock
 52      - const: bus_master # Master AXI clock
 53      - const: bus_slave # Slave AXI clock
 54      - const: slave_q2a # Slave Q2A clock
 55      - const: ddrss_sf_tbu # PCIe SF TBU clock
 56      - const: noc_aggr # Aggre NoC PCIe AXI clock
 57      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
 58      - const: qmip_pcie_ahb # QMIP PCIe AHB clock
 59
 60  interrupts:
 61    minItems: 8
 62    maxItems: 9
 63
 64  interrupt-names:
 65    minItems: 8
 66    items:
 67      - const: msi0
 68      - const: msi1
 69      - const: msi2
 70      - const: msi3
 71      - const: msi4
 72      - const: msi5
 73      - const: msi6
 74      - const: msi7
 75      - const: global
 76
 77  resets:
 78    minItems: 1
 79    maxItems: 2
 80
 81  reset-names:
 82    minItems: 1
 83    items:
 84      - const: pci # PCIe core reset
 85      - const: link_down # PCIe link down reset
 86
 87required:
 88  - power-domains
 89  - resets
 90  - reset-names
 91
 92allOf:
 93  - $ref: qcom,pcie-common.yaml#
 94
 95unevaluatedProperties: false
 96
 97examples:
 98  - |
 99    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
100    #include <dt-bindings/gpio/gpio.h>
101    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
102    #include <dt-bindings/interrupt-controller/arm-gic.h>
103
104    soc {
105        #address-cells = <2>;
106        #size-cells = <2>;
107
108        pcie@1c00000 {
109            compatible = "qcom,pcie-sm8550";
110            reg = <0 0x01c00000 0 0x3000>,
111                  <0 0x60000000 0 0xf1d>,
112                  <0 0x60000f20 0 0xa8>,
113                  <0 0x60001000 0 0x1000>,
114                  <0 0x60100000 0 0x100000>;
115            reg-names = "parf", "dbi", "elbi", "atu", "config";
116            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
117                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
118
119            bus-range = <0x00 0xff>;
120            device_type = "pci";
121            linux,pci-domain = <0>;
122            num-lanes = <2>;
123
124            #address-cells = <3>;
125            #size-cells = <2>;
126
127            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
128                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
129                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
130                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
131                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
132                     <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
133                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
134            clock-names = "aux",
135                          "cfg",
136                          "bus_master",
137                          "bus_slave",
138                          "slave_q2a",
139                          "ddrss_sf_tbu",
140                          "noc_aggr";
141
142            dma-coherent;
143
144            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
145                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
146                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
147                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
148                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
149                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
150                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
151                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
152                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
153            interrupt-names = "msi0", "msi1", "msi2", "msi3",
154                              "msi4", "msi5", "msi6", "msi7", "global";
155            #interrupt-cells = <1>;
156            interrupt-map-mask = <0 0 0 0x7>;
157            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
158                            <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
159                            <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
160                            <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
161
162            interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
163                            <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
164            interconnect-names = "pcie-mem", "cpu-pcie";
165
166            iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
167                        <0x100 &apps_smmu 0x1401 0x1>;
168
169            phys = <&pcie0_phy>;
170            phy-names = "pciephy";
171
172            pinctrl-0 = <&pcie0_default_state>;
173            pinctrl-names = "default";
174
175            power-domains = <&gcc PCIE_0_GDSC>;
176
177            resets = <&gcc GCC_PCIE_0_BCR>;
178            reset-names = "pci";
179
180            perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
181            wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
182        };
183    };