qcom,pcie-sm8450.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8450 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
 15  DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    enum:
 20      - qcom,pcie-sm8450-pcie0
 21      - qcom,pcie-sm8450-pcie1
 22
 23  reg:
 24    minItems: 5
 25    maxItems: 6
 26
 27  reg-names:
 28    minItems: 5
 29    items:
 30      - const: parf # Qualcomm specific registers
 31      - const: dbi # DesignWare PCIe registers
 32      - const: elbi # External local bus interface registers
 33      - const: atu # ATU address space
 34      - const: config # PCIe configuration space
 35      - const: mhi # MHI registers
 36
 37  clocks:
 38    minItems: 11
 39    maxItems: 12
 40
 41  clock-names:
 42    minItems: 11
 43    items:
 44      - const: pipe # PIPE clock
 45      - const: pipe_mux # PIPE MUX
 46      - const: phy_pipe # PIPE output clock
 47      - const: ref # REFERENCE clock
 48      - const: aux # Auxiliary clock
 49      - const: cfg # Configuration clock
 50      - const: bus_master # Master AXI clock
 51      - const: bus_slave # Slave AXI clock
 52      - const: slave_q2a # Slave Q2A clock
 53      - const: ddrss_sf_tbu # PCIe SF TBU clock
 54      - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock
 55      - const: aggre1 # Aggre NoC PCIe1 AXI clock
 56
 57  interrupts:
 58    minItems: 9
 59    maxItems: 9
 60
 61  interrupt-names:
 62    items:
 63      - const: msi0
 64      - const: msi1
 65      - const: msi2
 66      - const: msi3
 67      - const: msi4
 68      - const: msi5
 69      - const: msi6
 70      - const: msi7
 71      - const: global
 72
 73  resets:
 74    maxItems: 1
 75
 76  reset-names:
 77    items:
 78      - const: pci
 79
 80required:
 81  - power-domains
 82  - resets
 83  - reset-names
 84
 85allOf:
 86  - $ref: qcom,pcie-common.yaml#
 87
 88unevaluatedProperties: false
 89
 90examples:
 91  - |
 92    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
 93    #include <dt-bindings/clock/qcom,rpmh.h>
 94    #include <dt-bindings/gpio/gpio.h>
 95    #include <dt-bindings/interconnect/qcom,sm8450.h>
 96    #include <dt-bindings/interrupt-controller/arm-gic.h>
 97
 98    soc {
 99        #address-cells = <2>;
100        #size-cells = <2>;
101
102        pcie@1c00000 {
103            compatible = "qcom,pcie-sm8450-pcie0";
104            reg = <0 0x01c00000 0 0x3000>,
105                  <0 0x60000000 0 0xf1d>,
106                  <0 0x60000f20 0 0xa8>,
107                  <0 0x60001000 0 0x1000>,
108                  <0 0x60100000 0 0x100000>;
109            reg-names = "parf", "dbi", "elbi", "atu", "config";
110            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
111                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
112
113            bus-range = <0x00 0xff>;
114            device_type = "pci";
115            linux,pci-domain = <0>;
116            max-link-speed = <2>;
117            num-lanes = <1>;
118
119            #address-cells = <3>;
120            #size-cells = <2>;
121
122            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
123                     <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
124                     <&pcie0_phy>,
125                     <&rpmhcc RPMH_CXO_CLK>,
126                     <&gcc GCC_PCIE_0_AUX_CLK>,
127                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
128                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
129                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
130                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
131                     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
132                     <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
133                     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
134            clock-names = "pipe",
135                          "pipe_mux",
136                          "phy_pipe",
137                          "ref",
138                          "aux",
139                          "cfg",
140                          "bus_master",
141                          "bus_slave",
142                          "slave_q2a",
143                          "ddrss_sf_tbu",
144                          "aggre0",
145                          "aggre1";
146
147            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
148                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
149                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
150                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
151                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
152                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
153                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
154                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
155                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
156            interrupt-names = "msi0", "msi1", "msi2", "msi3",
157                              "msi4", "msi5", "msi6", "msi7", "global";
158            #interrupt-cells = <1>;
159            interrupt-map-mask = <0 0 0 0x7>;
160            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
161                            <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
162                            <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
163                            <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
164            msi-map = <0x0 &gic_its 0x5981 0x1>,
165                      <0x100 &gic_its 0x5980 0x1>;
166            msi-map-mask = <0xff00>;
167
168            iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
169                        <0x100 &apps_smmu 0x1c01 0x1>;
170
171            phys = <&pcie0_phy>;
172            phy-names = "pciephy";
173
174            pinctrl-0 = <&pcie0_default_state>;
175            pinctrl-names = "default";
176
177            power-domains = <&gcc PCIE_0_GDSC>;
178
179            resets = <&gcc GCC_PCIE_0_BCR>;
180            reset-names = "pci";
181
182            perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
183            wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
184        };
185    };