qcom,pcie-sm8350.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8350 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
 15  DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    const: qcom,pcie-sm8350
 20
 21  reg:
 22    minItems: 5
 23    maxItems: 6
 24
 25  reg-names:
 26    minItems: 5
 27    items:
 28      - const: parf # Qualcomm specific registers
 29      - const: dbi # DesignWare PCIe registers
 30      - const: elbi # External local bus interface registers
 31      - const: atu # ATU address space
 32      - const: config # PCIe configuration space
 33      - const: mhi # MHI registers
 34
 35  clocks:
 36    minItems: 8
 37    maxItems: 9
 38
 39  clock-names:
 40    minItems: 8
 41    items:
 42      - const: aux # Auxiliary clock
 43      - const: cfg # Configuration clock
 44      - const: bus_master # Master AXI clock
 45      - const: bus_slave # Slave AXI clock
 46      - const: slave_q2a # Slave Q2A clock
 47      - const: tbu # PCIe TBU clock
 48      - const: ddrss_sf_tbu # PCIe SF TBU clock
 49      - const: aggre1 # Aggre NoC PCIe1 AXI clock
 50      - const: aggre0 # Aggre NoC PCIe0 AXI clock
 51
 52  interrupts:
 53    minItems: 8
 54    maxItems: 9
 55
 56  interrupt-names:
 57    minItems: 8
 58    items:
 59      - const: msi0
 60      - const: msi1
 61      - const: msi2
 62      - const: msi3
 63      - const: msi4
 64      - const: msi5
 65      - const: msi6
 66      - const: msi7
 67      - const: global
 68
 69  resets:
 70    maxItems: 1
 71
 72  reset-names:
 73    items:
 74      - const: pci
 75
 76required:
 77  - power-domains
 78  - resets
 79  - reset-names
 80
 81allOf:
 82  - $ref: qcom,pcie-common.yaml#
 83
 84unevaluatedProperties: false
 85
 86examples:
 87  - |
 88    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
 89    #include <dt-bindings/gpio/gpio.h>
 90    #include <dt-bindings/interconnect/qcom,sm8350.h>
 91    #include <dt-bindings/interrupt-controller/arm-gic.h>
 92
 93    soc {
 94        #address-cells = <2>;
 95        #size-cells = <2>;
 96
 97        pcie@1c00000 {
 98            compatible = "qcom,pcie-sm8350";
 99            reg = <0 0x01c00000 0 0x3000>,
100                  <0 0x60000000 0 0xf1d>,
101                  <0 0x60000f20 0 0xa8>,
102                  <0 0x60001000 0 0x1000>,
103                  <0 0x60100000 0 0x100000>;
104            reg-names = "parf", "dbi", "elbi", "atu", "config";
105            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
106                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
107
108            bus-range = <0x00 0xff>;
109            device_type = "pci";
110            linux,pci-domain = <0>;
111            num-lanes = <1>;
112
113            #address-cells = <3>;
114            #size-cells = <2>;
115
116            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
117                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
118                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
119                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
120                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
121                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
122                     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
123                     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
124                     <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
125            clock-names = "aux",
126                          "cfg",
127                          "bus_master",
128                          "bus_slave",
129                          "slave_q2a",
130                          "tbu",
131                          "ddrss_sf_tbu",
132                          "aggre1",
133                          "aggre0";
134
135            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
143                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
144            interrupt-names = "msi0", "msi1", "msi2", "msi3",
145                              "msi4", "msi5", "msi6", "msi7", "global";
146            #interrupt-cells = <1>;
147            interrupt-map-mask = <0 0 0 0x7>;
148            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
149                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
150                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
151                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
152
153            iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
154                        <0x100 &apps_smmu 0x1c01 0x1>;
155
156            phys = <&pcie0_phy>;
157            phy-names = "pciephy";
158
159            pinctrl-0 = <&pcie0_default_state>;
160            pinctrl-names = "default";
161
162            power-domains = <&gcc PCIE_0_GDSC>;
163
164            resets = <&gcc GCC_PCIE_0_BCR>;
165            reset-names = "pci";
166
167            perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
168            wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
169        };
170    };