qcom,pcie-sm8250.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8250 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
 15  DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    const: qcom,pcie-sm8250
 20
 21  reg:
 22    minItems: 5
 23    maxItems: 6
 24
 25  reg-names:
 26    minItems: 5
 27    items:
 28      - const: parf # Qualcomm specific registers
 29      - const: dbi # DesignWare PCIe registers
 30      - const: elbi # External local bus interface registers
 31      - const: atu # ATU address space
 32      - const: config # PCIe configuration space
 33      - const: mhi # MHI registers
 34
 35  clocks:
 36    minItems: 8
 37    maxItems: 9
 38
 39  clock-names:
 40    # Unfortunately the "optional" ref clock is used in the middle of the list
 41    oneOf:
 42      - items:
 43          - const: pipe # PIPE clock
 44          - const: aux # Auxiliary clock
 45          - const: cfg # Configuration clock
 46          - const: bus_master # Master AXI clock
 47          - const: bus_slave # Slave AXI clock
 48          - const: slave_q2a # Slave Q2A clock
 49          - const: ref # REFERENCE clock
 50          - const: tbu # PCIe TBU clock
 51          - const: ddrss_sf_tbu # PCIe SF TBU clock
 52      - items:
 53          - const: pipe # PIPE clock
 54          - const: aux # Auxiliary clock
 55          - const: cfg # Configuration clock
 56          - const: bus_master # Master AXI clock
 57          - const: bus_slave # Slave AXI clock
 58          - const: slave_q2a # Slave Q2A clock
 59          - const: tbu # PCIe TBU clock
 60          - const: ddrss_sf_tbu # PCIe SF TBU clock
 61
 62  interrupts:
 63    minItems: 8
 64    maxItems: 9
 65
 66  interrupt-names:
 67    minItems: 8
 68    items:
 69      - const: msi0
 70      - const: msi1
 71      - const: msi2
 72      - const: msi3
 73      - const: msi4
 74      - const: msi5
 75      - const: msi6
 76      - const: msi7
 77      - const: global
 78
 79  resets:
 80    maxItems: 1
 81
 82  reset-names:
 83    items:
 84      - const: pci
 85
 86required:
 87  - power-domains
 88  - resets
 89  - reset-names
 90
 91allOf:
 92  - $ref: qcom,pcie-common.yaml#
 93
 94unevaluatedProperties: false
 95
 96examples:
 97  - |
 98    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 99    #include <dt-bindings/gpio/gpio.h>
100    #include <dt-bindings/interconnect/qcom,sm8250.h>
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102
103    soc {
104        #address-cells = <2>;
105        #size-cells = <2>;
106
107        pcie@1c00000 {
108            compatible = "qcom,pcie-sm8250";
109            reg = <0 0x01c00000 0 0x3000>,
110                  <0 0x60000000 0 0xf1d>,
111                  <0 0x60000f20 0 0xa8>,
112                  <0 0x60001000 0 0x1000>,
113                  <0 0x60100000 0 0x100000>,
114                  <0 0x01c03000 0 0x1000>;
115            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
116            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
117                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
118
119            bus-range = <0x00 0xff>;
120            device_type = "pci";
121            linux,pci-domain = <0>;
122            num-lanes = <1>;
123
124            #address-cells = <3>;
125            #size-cells = <2>;
126
127            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
128                     <&gcc GCC_PCIE_0_AUX_CLK>,
129                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
130                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
131                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
132                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
133                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
134                     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
135            clock-names = "pipe",
136                          "aux",
137                          "cfg",
138                          "bus_master",
139                          "bus_slave",
140                          "slave_q2a",
141                          "tbu",
142                          "ddrss_sf_tbu";
143
144            dma-coherent;
145
146            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
147                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
148                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
149                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
150                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
151                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
152                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
153                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
154                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
155            interrupt-names = "msi0", "msi1", "msi2", "msi3",
156                              "msi4", "msi5", "msi6", "msi7", "global";
157            #interrupt-cells = <1>;
158            interrupt-map-mask = <0 0 0 0x7>;
159            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
160                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
161                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
162                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
163
164            iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
165                        <0x100 &apps_smmu 0x1c01 0x1>;
166
167            phys = <&pcie0_phy>;
168            phy-names = "pciephy";
169
170            pinctrl-0 = <&pcie0_default_state>;
171            pinctrl-names = "default";
172
173            power-domains = <&gcc PCIE_0_GDSC>;
174
175            resets = <&gcc GCC_PCIE_0_BCR>;
176            reset-names = "pci";
177
178            perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
179            wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
180        };
181    };