qcom,pcie-sm8150.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8150 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
 15  DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - const: qcom,pcie-sm8150
 21      - items:
 22          - enum:
 23              - qcom,pcie-qcs615
 24          - const: qcom,pcie-sm8150
 25
 26  reg:
 27    minItems: 5
 28    maxItems: 6
 29
 30  reg-names:
 31    minItems: 5
 32    items:
 33      - const: parf # Qualcomm specific registers
 34      - const: dbi # DesignWare PCIe registers
 35      - const: elbi # External local bus interface registers
 36      - const: atu # ATU address space
 37      - const: config # PCIe configuration space
 38      - const: mhi # MHI registers
 39
 40  clocks:
 41    minItems: 6
 42    maxItems: 6
 43
 44  clock-names:
 45    items:
 46      - const: pipe # PIPE clock
 47      - const: aux # Auxiliary clock
 48      - const: cfg # Configuration clock
 49      - const: bus_master # Master AXI clock
 50      - const: bus_slave # Slave AXI clock
 51      - const: slave_q2a # Slave Q2A clock
 52
 53  interrupts:
 54    minItems: 8
 55    maxItems: 9
 56
 57  interrupt-names:
 58    minItems: 8
 59    items:
 60      - const: msi0
 61      - const: msi1
 62      - const: msi2
 63      - const: msi3
 64      - const: msi4
 65      - const: msi5
 66      - const: msi6
 67      - const: msi7
 68      - const: global
 69
 70  resets:
 71    maxItems: 1
 72
 73  reset-names:
 74    items:
 75      - const: pci
 76
 77required:
 78  - power-domains
 79  - resets
 80  - reset-names
 81
 82allOf:
 83  - $ref: qcom,pcie-common.yaml#
 84
 85unevaluatedProperties: false
 86
 87examples:
 88  - |
 89    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
 90    #include <dt-bindings/clock/qcom,rpmh.h>
 91    #include <dt-bindings/gpio/gpio.h>
 92    #include <dt-bindings/interconnect/qcom,sm8150.h>
 93    #include <dt-bindings/interrupt-controller/arm-gic.h>
 94
 95    soc {
 96        #address-cells = <2>;
 97        #size-cells = <2>;
 98        pcie@1c00000 {
 99            compatible = "qcom,pcie-sm8150";
100            reg = <0 0x01c00000 0 0x3000>,
101                  <0 0x60000000 0 0xf1d>,
102                  <0 0x60000f20 0 0xa8>,
103                  <0 0x60001000 0 0x1000>,
104                  <0 0x60100000 0 0x100000>;
105            reg-names = "parf", "dbi", "elbi", "atu", "config";
106            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
107                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
108
109            bus-range = <0x00 0xff>;
110            device_type = "pci";
111            linux,pci-domain = <0>;
112            num-lanes = <1>;
113
114            #address-cells = <3>;
115            #size-cells = <2>;
116
117            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
118                     <&gcc GCC_PCIE_0_AUX_CLK>,
119                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
120                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
121                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
122                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
123            clock-names = "pipe",
124                          "aux",
125                          "cfg",
126                          "bus_master",
127                          "bus_slave",
128                          "slave_q2a";
129
130            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
131                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
132                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
133                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
134                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
135                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
139            interrupt-names = "msi0", "msi1", "msi2", "msi3",
140                              "msi4", "msi5", "msi6", "msi7", "global";
141            #interrupt-cells = <1>;
142            interrupt-map-mask = <0 0 0 0x7>;
143            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
144                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
145                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
146                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
147
148            iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
149                        <0x100 &apps_smmu 0x1d81 0x1>;
150
151            phys = <&pcie0_phy>;
152            phy-names = "pciephy";
153
154            pinctrl-0 = <&pcie0_default_state>;
155            pinctrl-names = "default";
156
157            power-domains = <&gcc PCIE_0_GDSC>;
158
159            resets = <&gcc GCC_PCIE_0_BCR>;
160            reset-names = "pci";
161
162            perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
163            wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
164        };
165    };