qcom,pcie-sc7280.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SC7280 PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
 15  DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    const: qcom,pcie-sc7280
 20
 21  reg:
 22    minItems: 5
 23    maxItems: 6
 24
 25  reg-names:
 26    minItems: 5
 27    items:
 28      - const: parf # Qualcomm specific registers
 29      - const: dbi # DesignWare PCIe registers
 30      - const: elbi # External local bus interface registers
 31      - const: atu # ATU address space
 32      - const: config # PCIe configuration space
 33      - const: mhi # MHI registers
 34
 35  clocks:
 36    minItems: 13
 37    maxItems: 13
 38
 39  clock-names:
 40    items:
 41      - const: pipe # PIPE clock
 42      - const: pipe_mux # PIPE MUX
 43      - const: phy_pipe # PIPE output clock
 44      - const: ref # REFERENCE clock
 45      - const: aux # Auxiliary clock
 46      - const: cfg # Configuration clock
 47      - const: bus_master # Master AXI clock
 48      - const: bus_slave # Slave AXI clock
 49      - const: slave_q2a # Slave Q2A clock
 50      - const: tbu # PCIe TBU clock
 51      - const: ddrss_sf_tbu # PCIe SF TBU clock
 52      - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
 53      - const: aggre1 # Aggre NoC PCIe1 AXI clock
 54
 55  interrupts:
 56    minItems: 8
 57    maxItems: 9
 58
 59  interrupt-names:
 60    minItems: 8
 61    items:
 62      - const: msi0
 63      - const: msi1
 64      - const: msi2
 65      - const: msi3
 66      - const: msi4
 67      - const: msi5
 68      - const: msi6
 69      - const: msi7
 70      - const: global
 71
 72  resets:
 73    maxItems: 1
 74
 75  reset-names:
 76    items:
 77      - const: pci
 78
 79required:
 80  - power-domains
 81  - resets
 82  - reset-names
 83
 84allOf:
 85  - $ref: qcom,pcie-common.yaml#
 86
 87unevaluatedProperties: false
 88
 89examples:
 90  - |
 91    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 92    #include <dt-bindings/clock/qcom,rpmh.h>
 93    #include <dt-bindings/gpio/gpio.h>
 94    #include <dt-bindings/interrupt-controller/arm-gic.h>
 95
 96    soc {
 97        #address-cells = <2>;
 98        #size-cells = <2>;
 99
100        pcie@1c08000 {
101            compatible = "qcom,pcie-sc7280";
102            reg = <0 0x01c08000 0 0x3000>,
103                  <0 0x40000000 0 0xf1d>,
104                  <0 0x40000f20 0 0xa8>,
105                  <0 0x40001000 0 0x1000>,
106                  <0 0x40100000 0 0x100000>;
107            reg-names = "parf", "dbi", "elbi", "atu", "config";
108            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
109                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
110
111            bus-range = <0x00 0xff>;
112            device_type = "pci";
113            linux,pci-domain = <1>;
114            num-lanes = <2>;
115
116            #address-cells = <3>;
117            #size-cells = <2>;
118
119            assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
120            assigned-clock-rates = <19200000>;
121
122            clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
123                     <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
124                     <&pcie1_phy>,
125                     <&rpmhcc RPMH_CXO_CLK>,
126                     <&gcc GCC_PCIE_1_AUX_CLK>,
127                     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
128                     <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
129                     <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
130                     <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
131                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
132                     <&gcc GCC_DDRSS_PCIE_SF_CLK>,
133                     <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
134                     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
135
136            clock-names = "pipe",
137                          "pipe_mux",
138                          "phy_pipe",
139                          "ref",
140                          "aux",
141                          "cfg",
142                          "bus_master",
143                          "bus_slave",
144                          "slave_q2a",
145                          "tbu",
146                          "ddrss_sf_tbu",
147                          "aggre0",
148                          "aggre1";
149
150            dma-coherent;
151
152            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
153                         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
154                         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
155                         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
156                         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
157                         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
158                         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
159                         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
160                         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
161            interrupt-names = "msi0", "msi1", "msi2", "msi3",
162                              "msi4", "msi5", "msi6", "msi7", "global";
163            #interrupt-cells = <1>;
164            interrupt-map-mask = <0 0 0 0x7>;
165            interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
166                            <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
167                            <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
168                            <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
169
170            iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
171                        <0x100 &apps_smmu 0x1c81 0x1>;
172
173            pinctrl-names = "default";
174            pinctrl-0 = <&pcie1_clkreq_n>;
175
176            power-domains = <&gcc GCC_PCIE_1_GDSC>;
177
178            resets = <&gcc GCC_PCIE_1_BCR>;
179            reset-names = "pci";
180
181            vddpe-3v3-supply = <&pp3300_ssd>;
182            pcie1_port0: pcie@0 {
183                device_type = "pci";
184                reg = <0x0 0x0 0x0 0x0 0x0>;
185                bus-range = <0x01 0xff>;
186
187                #address-cells = <3>;
188                #size-cells = <2>;
189                ranges;
190                phys = <&pcie1_phy>;
191
192                reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
193            };
194        };
195    };