qcom,pcie-sa8775p.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SA8775p PCI Express Root Complex
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Manivannan Sadhasivam <mani@kernel.org>
 12
 13description:
 14  Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
 15  DesignWare PCIe IP.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - const: qcom,pcie-sa8775p
 21      - items:
 22          - enum:
 23              - qcom,pcie-qcs8300
 24          - const: qcom,pcie-sa8775p
 25
 26  reg:
 27    minItems: 6
 28    maxItems: 6
 29
 30  reg-names:
 31    items:
 32      - const: parf # Qualcomm specific registers
 33      - const: dbi # DesignWare PCIe registers
 34      - const: elbi # External local bus interface registers
 35      - const: atu # ATU address space
 36      - const: config # PCIe configuration space
 37      - const: mhi # MHI registers
 38
 39  clocks:
 40    minItems: 5
 41    maxItems: 5
 42
 43  clock-names:
 44    items:
 45      - const: aux # Auxiliary clock
 46      - const: cfg # Configuration clock
 47      - const: bus_master # Master AXI clock
 48      - const: bus_slave # Slave AXI clock
 49      - const: slave_q2a # Slave Q2A clock
 50
 51  interrupts:
 52    minItems: 8
 53    maxItems: 9
 54
 55  interrupt-names:
 56    minItems: 8
 57    items:
 58      - const: msi0
 59      - const: msi1
 60      - const: msi2
 61      - const: msi3
 62      - const: msi4
 63      - const: msi5
 64      - const: msi6
 65      - const: msi7
 66      - const: global
 67
 68  resets:
 69    items:
 70      - description: PCIe controller reset
 71      - description: PCIe link down reset
 72
 73  reset-names:
 74    items:
 75      - const: pci
 76      - const: link_down
 77
 78required:
 79  - interconnects
 80  - interconnect-names
 81  - power-domains
 82  - resets
 83  - reset-names
 84
 85allOf:
 86  - $ref: qcom,pcie-common.yaml#
 87
 88unevaluatedProperties: false
 89
 90examples:
 91  - |
 92    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
 93    #include <dt-bindings/clock/qcom,rpmh.h>
 94    #include <dt-bindings/gpio/gpio.h>
 95    #include <dt-bindings/interrupt-controller/arm-gic.h>
 96    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
 97
 98    soc {
 99        #address-cells = <2>;
100        #size-cells = <2>;
101
102        pcie@1c00000 {
103            compatible = "qcom,pcie-sa8775p";
104            reg = <0x0 0x01c00000 0x0 0x3000>,
105                  <0x0 0x40000000 0x0 0xf20>,
106                  <0x0 0x40000f20 0x0 0xa8>,
107                  <0x0 0x40001000 0x0 0x4000>,
108                  <0x0 0x40100000 0x0 0x100000>,
109                  <0x0 0x01c03000 0x0 0x1000>;
110            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
111            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
112                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
113
114            bus-range = <0x00 0xff>;
115            device_type = "pci";
116            linux,pci-domain = <0>;
117            num-lanes = <2>;
118
119            #address-cells = <3>;
120            #size-cells = <2>;
121
122            assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
123            assigned-clock-rates = <19200000>;
124
125            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
126                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
127                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
128                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
129                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
130            clock-names = "aux",
131                          "cfg",
132                          "bus_master",
133                          "bus_slave",
134                          "slave_q2a";
135
136            dma-coherent;
137
138            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
143                         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
144                         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
145                         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
146                         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
147            interrupt-names = "msi0",
148                              "msi1",
149                              "msi2",
150                              "msi3",
151                              "msi4",
152                              "msi5",
153                              "msi6",
154                              "msi7",
155                              "global";
156            #interrupt-cells = <1>;
157            interrupt-map-mask = <0 0 0 0x7>;
158            interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
159                            <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
160                            <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
161                            <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
162
163            interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
164                            <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
165            interconnect-names = "pcie-mem", "cpu-pcie";
166
167            iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
168                        <0x100 &pcie_smmu 0x0001 0x1>;
169
170            phys = <&pcie0_phy>;
171            phy-names = "pciephy";
172
173            power-domains = <&gcc PCIE_0_GDSC>;
174
175            resets = <&gcc GCC_PCIE_0_BCR>,
176                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
177            reset-names = "pci",
178                          "link_down";
179
180            perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
181            wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
182        };
183    };