mediatek-pcie-mt7623.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: PCIe controller on MediaTek SoCs
  8
  9maintainers:
 10  - Christian Marangi <ansuelsmth@gmail.com>
 11
 12properties:
 13  compatible:
 14    enum:
 15      - mediatek,mt2701-pcie
 16      - mediatek,mt7623-pcie
 17
 18  reg:
 19    minItems: 4
 20    maxItems: 4
 21
 22  reg-names:
 23    items:
 24      - const: subsys
 25      - const: port0
 26      - const: port1
 27      - const: port2
 28
 29  clocks:
 30    minItems: 4
 31    maxItems: 4
 32
 33  clock-names:
 34    items:
 35      - const: free_ck
 36      - const: sys_ck0
 37      - const: sys_ck1
 38      - const: sys_ck2
 39
 40  resets:
 41    minItems: 3
 42    maxItems: 3
 43
 44  reset-names:
 45    items:
 46      - const: pcie-rst0
 47      - const: pcie-rst1
 48      - const: pcie-rst2
 49
 50  phys:
 51    minItems: 3
 52    maxItems: 3
 53
 54  phy-names:
 55    items:
 56      - const: pcie-phy0
 57      - const: pcie-phy1
 58      - const: pcie-phy2
 59
 60  power-domains:
 61    maxItems: 1
 62
 63required:
 64  - compatible
 65  - reg
 66  - reg-names
 67  - ranges
 68  - clocks
 69  - clock-names
 70  - '#interrupt-cells'
 71  - resets
 72  - reset-names
 73  - phys
 74  - phy-names
 75  - power-domains
 76  - pcie@0,0
 77  - pcie@1,0
 78  - pcie@2,0
 79
 80allOf:
 81  - $ref: /schemas/pci/pci-host-bridge.yaml#
 82
 83unevaluatedProperties: false
 84
 85examples:
 86  # MT7623
 87  - |
 88    #include <dt-bindings/interrupt-controller/arm-gic.h>
 89    #include <dt-bindings/interrupt-controller/irq.h>
 90    #include <dt-bindings/clock/mt2701-clk.h>
 91    #include <dt-bindings/reset/mt2701-resets.h>
 92    #include <dt-bindings/phy/phy.h>
 93    #include <dt-bindings/power/mt2701-power.h>
 94
 95    soc {
 96        #address-cells = <2>;
 97        #size-cells = <2>;
 98
 99        pcie@1a140000 {
100            compatible = "mediatek,mt7623-pcie";
101            device_type = "pci";
102            reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
103                  <0 0x1a142000 0 0x1000>, /* Port0 registers */
104                  <0 0x1a143000 0 0x1000>, /* Port1 registers */
105                  <0 0x1a144000 0 0x1000>; /* Port2 registers */
106            reg-names = "subsys", "port0", "port1", "port2";
107            #address-cells = <3>;
108            #size-cells = <2>;
109            #interrupt-cells = <1>;
110            interrupt-map-mask = <0xf800 0 0 0>;
111            interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
112                            <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
113                            <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
114            clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
115                    <&hifsys CLK_HIFSYS_PCIE0>,
116                    <&hifsys CLK_HIFSYS_PCIE1>,
117                    <&hifsys CLK_HIFSYS_PCIE2>;
118            clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
119            resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
120                     <&hifsys MT2701_HIFSYS_PCIE1_RST>,
121                     <&hifsys MT2701_HIFSYS_PCIE2_RST>;
122            reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
123            phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
124                   <&pcie2_phy PHY_TYPE_PCIE>;
125            phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
126            power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
127            bus-range = <0x00 0xff>;
128            ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>,	/* I/O space */
129                     <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */
130
131            pcie@0,0 {
132                device_type = "pci";
133                reg = <0x0000 0 0 0 0>;
134                #address-cells = <3>;
135                #size-cells = <2>;
136                #interrupt-cells = <1>;
137                interrupt-map-mask = <0 0 0 0>;
138                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
139                ranges;
140            };
141
142            pcie@1,0 {
143                device_type = "pci";
144                reg = <0x0800 0 0 0 0>;
145                #address-cells = <3>;
146                #size-cells = <2>;
147                #interrupt-cells = <1>;
148                interrupt-map-mask = <0 0 0 0>;
149                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
150                ranges;
151            };
152
153            pcie@2,0 {
154                device_type = "pci";
155                reg = <0x1000 0 0 0 0>;
156                #address-cells = <3>;
157                #size-cells = <2>;
158                #interrupt-cells = <1>;
159                interrupt-map-mask = <0 0 0 0>;
160                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
161                ranges;
162            };
163        };
164    };