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marvell,kirkwood-pcie.yaml
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linux-6.19.14/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml
1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Marvell EBU PCIe interfaces 8 9maintainers: 10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com> 11 - Pali Rohár <pali@kernel.org> 12 13allOf: 14 - $ref: /schemas/pci/pci-host-bridge.yaml# 15 16properties: 17 compatible: 18 enum: 19 - marvell,armada-370-pcie 20 - marvell,armada-xp-pcie 21 - marvell,dove-pcie 22 - marvell,kirkwood-pcie 23 24 ranges: 25 description: > 26 The ranges describing the MMIO registers have the following layout: 27 28 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 29 30 where: 31 32 * r is a 32-bits value that gives the offset of the MMIO registers of 33 this PCIe interface, from the base of the internal registers. 34 35 * s is a 32-bits value that give the size of this MMIO registers area. 36 This range entry translates the '0x82000000 0 r' PCI address into the 37 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal 38 register window (as identified by MBUS_ID(0xf0, 0x01)). 39 40 The ranges describing the MBus windows have the following layout: 41 42 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 43 44 where: 45 46 * t is the type of the MBus window (as defined by the standard PCI DT 47 bindings), 1 for I/O and 2 for memory. 48 49 * s is the PCI slot that corresponds to this PCIe interface 50 51 * w is the 'target ID' value for the MBus window 52 53 * a the 'attribute' value for the MBus window. 54 55 Since the location and size of the different MBus windows is not fixed in 56 hardware, and only determined in runtime, those ranges cover the full first 57 4 GB of the physical address space, and do not translate into a valid CPU 58 address. 59 60 msi-parent: 61 maxItems: 1 62 63patternProperties: 64 '^pcie@': 65 type: object 66 allOf: 67 - $ref: /schemas/pci/pci-bus-common.yaml# 68 - $ref: /schemas/pci/pci-device.yaml# 69 unevaluatedProperties: false 70 71 properties: 72 clocks: 73 maxItems: 1 74 75 interrupts: 76 minItems: 1 77 maxItems: 2 78 79 interrupt-names: 80 minItems: 1 81 items: 82 - const: intx 83 - const: error 84 85 reset-delay-us: 86 default: 100000 87 description: todo 88 89 marvell,pcie-port: 90 $ref: /schemas/types.yaml#/definitions/uint32 91 maximum: 3 92 description: todo 93 94 marvell,pcie-lane: 95 $ref: /schemas/types.yaml#/definitions/uint32 96 maximum: 3 97 description: todo 98 99 interrupt-controller: 100 type: object 101 additionalProperties: false 102 103 properties: 104 '#address-cells': 105 const: 0 106 107 interrupt-controller: true 108 109 '#interrupt-cells': 110 const: 1 111 112 required: 113 - assigned-addresses 114 - clocks 115 - interrupt-map 116 - marvell,pcie-port 117 118unevaluatedProperties: false 119 120examples: 121 - | 122 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 123 124 soc { 125 #address-cells = <2>; 126 #size-cells = <2>; 127 128 pcie@f001000000000000 { 129 compatible = "marvell,armada-xp-pcie"; 130 device_type = "pci"; 131 132 #address-cells = <3>; 133 #size-cells = <2>; 134 135 bus-range = <0x00 0xff>; 136 msi-parent = <&mpic>; 137 138 ranges = 139 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 140 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 141 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 142 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 143 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 144 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 145 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 146 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 147 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 148 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 149 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 150 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 151 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 152 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 153 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 154 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 155 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 156 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 157 158 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 159 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 160 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 161 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 162 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 163 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 164 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 165 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 166 167 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 168 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 169 170 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 171 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 172 173 pcie@1,0 { 174 device_type = "pci"; 175 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 176 reg = <0x0800 0 0 0 0>; 177 #address-cells = <3>; 178 #size-cells = <2>; 179 #interrupt-cells = <1>; 180 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 181 0x81000000 0 0 0x81000000 0x1 0 1 0>; 182 interrupt-map-mask = <0 0 0 0>; 183 interrupt-map = <0 0 0 0 &mpic 58>; 184 marvell,pcie-port = <0>; 185 marvell,pcie-lane = <0>; 186 num-lanes = <1>; 187 /* low-active PERST# reset on GPIO 25 */ 188 reset-gpios = <&gpio0 25 1>; 189 /* wait 20ms for device settle after reset deassertion */ 190 reset-delay-us = <20000>; 191 clocks = <&gateclk 5>; 192 }; 193 194 pcie@2,0 { 195 device_type = "pci"; 196 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 197 reg = <0x1000 0 0 0 0>; 198 #address-cells = <3>; 199 #size-cells = <2>; 200 #interrupt-cells = <1>; 201 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 202 0x81000000 0 0 0x81000000 0x2 0 1 0>; 203 interrupt-map-mask = <0 0 0 0>; 204 interrupt-map = <0 0 0 0 &mpic 59>; 205 marvell,pcie-port = <0>; 206 marvell,pcie-lane = <1>; 207 num-lanes = <1>; 208 clocks = <&gateclk 6>; 209 }; 210 211 pcie@3,0 { 212 device_type = "pci"; 213 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 214 reg = <0x1800 0 0 0 0>; 215 #address-cells = <3>; 216 #size-cells = <2>; 217 #interrupt-cells = <1>; 218 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 219 0x81000000 0 0 0x81000000 0x3 0 1 0>; 220 interrupt-map-mask = <0 0 0 0>; 221 interrupt-map = <0 0 0 0 &mpic 60>; 222 marvell,pcie-port = <0>; 223 marvell,pcie-lane = <2>; 224 num-lanes = <1>; 225 clocks = <&gateclk 7>; 226 }; 227 228 pcie@4,0 { 229 device_type = "pci"; 230 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 231 reg = <0x2000 0 0 0 0>; 232 #address-cells = <3>; 233 #size-cells = <2>; 234 #interrupt-cells = <1>; 235 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 236 0x81000000 0 0 0x81000000 0x4 0 1 0>; 237 interrupt-map-mask = <0 0 0 0>; 238 interrupt-map = <0 0 0 0 &mpic 61>; 239 marvell,pcie-port = <0>; 240 marvell,pcie-lane = <3>; 241 num-lanes = <1>; 242 clocks = <&gateclk 8>; 243 }; 244 245 pcie@5,0 { 246 device_type = "pci"; 247 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 248 reg = <0x2800 0 0 0 0>; 249 #address-cells = <3>; 250 #size-cells = <2>; 251 #interrupt-cells = <1>; 252 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 253 0x81000000 0 0 0x81000000 0x5 0 1 0>; 254 interrupt-map-mask = <0 0 0 0>; 255 interrupt-map = <0 0 0 0 &mpic 62>; 256 marvell,pcie-port = <1>; 257 marvell,pcie-lane = <0>; 258 num-lanes = <1>; 259 clocks = <&gateclk 9>; 260 }; 261 262 pcie@6,0 { 263 device_type = "pci"; 264 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 265 reg = <0x3000 0 0 0 0>; 266 #address-cells = <3>; 267 #size-cells = <2>; 268 #interrupt-cells = <1>; 269 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 270 0x81000000 0 0 0x81000000 0x6 0 1 0>; 271 interrupt-map-mask = <0 0 0 0>; 272 interrupt-map = <0 0 0 0 &mpic 63>; 273 marvell,pcie-port = <1>; 274 marvell,pcie-lane = <1>; 275 num-lanes = <1>; 276 clocks = <&gateclk 10>; 277 }; 278 }; 279 }; 280...
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