marvell,armada8k-pcie.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Marvell Armada 7K/8K PCIe interface
  8
  9maintainers:
 10  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 11
 12description:
 13  This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
 14
 15select:
 16  properties:
 17    compatible:
 18      contains:
 19        enum:
 20          - marvell,armada8k-pcie
 21  required:
 22    - compatible
 23
 24allOf:
 25  - $ref: snps,dw-pcie.yaml#
 26
 27properties:
 28  compatible:
 29    items:
 30      - enum:
 31          - marvell,armada8k-pcie
 32      - const: snps,dw-pcie
 33
 34  reg:
 35    maxItems: 2
 36
 37  reg-names:
 38    items:
 39      - const: ctrl
 40      - const: config
 41
 42  clocks:
 43    minItems: 1
 44    maxItems: 2
 45
 46  clock-names:
 47    items:
 48      - const: core
 49      - const: reg
 50
 51  interrupts:
 52    maxItems: 1
 53
 54  msi-parent:
 55    maxItems: 1
 56
 57  phys:
 58    minItems: 1
 59    maxItems: 4
 60
 61  phy-names:
 62    minItems: 1
 63    maxItems: 4
 64
 65  marvell,reset-gpio:
 66    maxItems: 1
 67    deprecated: true
 68
 69required:
 70  - interrupt-map
 71  - clocks
 72  - msi-parent
 73
 74unevaluatedProperties: false
 75
 76examples:
 77  - |
 78    #include <dt-bindings/interrupt-controller/arm-gic.h>
 79    #include <dt-bindings/interrupt-controller/irq.h>
 80
 81    pcie@f2600000 {
 82        compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 83        reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;
 84        reg-names = "ctrl", "config";
 85        #address-cells = <3>;
 86        #size-cells = <2>;
 87        #interrupt-cells = <1>;
 88        device_type = "pci";
 89        dma-coherent;
 90        msi-parent = <&gic_v2m0>;
 91
 92        ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>,  /* downstream I/O */
 93                 <0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>;  /* non-prefetchable memory */
 94        interrupt-map-mask = <0 0 0 0>;
 95        interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 96        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 97        num-lanes = <1>;
 98        clocks = <&cpm_syscon0 1 13>;
 99    };
100...