marvell,armada-3700-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/marvell,armada-3700-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Marvell Armada 3700 (Aardvark) PCIe Controller
  8
  9maintainers:
 10  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 11  - Pali Rohár <pali@kernel.org>
 12
 13allOf:
 14  - $ref: /schemas/pci/pci-host-bridge.yaml#
 15
 16properties:
 17  compatible:
 18    const: marvell,armada-3700-pcie
 19
 20  reg:
 21    maxItems: 1
 22
 23  clocks:
 24    maxItems: 1
 25
 26  interrupts:
 27    maxItems: 1
 28
 29  msi-controller: true
 30
 31  msi-parent:
 32    maxItems: 1
 33
 34  phys:
 35    maxItems: 1
 36
 37  reset-gpios:
 38    description: PCIe reset GPIO signals.
 39
 40  interrupt-controller:
 41    type: object
 42    additionalProperties: false
 43
 44    properties:
 45      '#address-cells':
 46        const: 0
 47
 48      interrupt-controller: true
 49
 50      '#interrupt-cells':
 51        const: 1
 52
 53    required:
 54      - interrupt-controller
 55      - '#interrupt-cells'
 56
 57required:
 58  - compatible
 59  - reg
 60  - interrupts
 61  - '#interrupt-cells'
 62
 63unevaluatedProperties: false
 64
 65examples:
 66  - |
 67    #include <dt-bindings/interrupt-controller/arm-gic.h>
 68    #include <dt-bindings/gpio/gpio.h>
 69
 70    bus {
 71        #address-cells = <2>;
 72        #size-cells = <2>;
 73
 74        pcie@d0070000 {
 75            compatible = "marvell,armada-3700-pcie";
 76            device_type = "pci";
 77            reg = <0 0xd0070000 0 0x20000>;
 78            #address-cells = <3>;
 79            #size-cells = <2>;
 80            bus-range = <0x00 0xff>;
 81            interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 82            msi-controller;
 83            msi-parent = <&pcie0>;
 84            ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000>,
 85                    <0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>;
 86
 87            #interrupt-cells = <1>;
 88            interrupt-map-mask = <0 0 0 7>;
 89            interrupt-map = <0 0 0 1 &pcie_intc 0>,
 90                            <0 0 0 2 &pcie_intc 1>,
 91                            <0 0 0 3 &pcie_intc 2>,
 92                            <0 0 0 4 &pcie_intc 3>;
 93            phys = <&comphy1 0>;
 94            max-link-speed = <2>;
 95            reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 96
 97            pcie_intc: interrupt-controller {
 98                #address-cells = <0>;
 99                interrupt-controller;
100                #interrupt-cells = <1>;
101            };
102        };
103    };