fsl,layerscape-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale Layerscape PCIe Root Complex(RC) controller
  8
  9maintainers:
 10  - Frank Li <Frank.Li@nxp.com>
 11
 12description:
 13  This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
 14
 15  This controller derives its clocks from the Reset Configuration Word (RCW)
 16  which is used to describe the PLL settings at the time of chip-reset.
 17
 18  Also as per the available Reference Manuals, there is no specific 'version'
 19  register available in the Freescale PCIe controller register set,
 20  which can allow determining the underlying DesignWare PCIe controller version
 21  information.
 22
 23properties:
 24  compatible:
 25    oneOf:
 26      - enum:
 27          - fsl,ls1012a-pcie
 28          - fsl,ls1021a-pcie
 29          - fsl,ls1028a-pcie
 30          - fsl,ls1043a-pcie
 31          - fsl,ls1046a-pcie
 32          - fsl,ls1088a-pcie
 33          - fsl,ls2080a-pcie
 34          - fsl,ls2085a-pcie
 35          - fsl,ls2088a-pcie
 36      - items:
 37          - const: fsl,lx2160ar2-pcie
 38          - const: fsl,ls2088a-pcie
 39  reg:
 40    maxItems: 2
 41
 42  reg-names:
 43    items:
 44      - const: regs
 45      - const: config
 46
 47  fsl,pcie-scfg:
 48    $ref: /schemas/types.yaml#/definitions/phandle-array
 49    description: A phandle to the SCFG device node. The second entry is the
 50      physical PCIe controller index starting from '0'. This is used to get
 51      SCFG PEXN registers.
 52    items:
 53      items:
 54        - description: A phandle to the SCFG device node
 55        - description: PCIe controller index starting from '0'
 56    maxItems: 1
 57
 58  big-endian:
 59    $ref: /schemas/types.yaml#/definitions/flag
 60    description: If the PEX_LUT and PF register block is in big-endian, specify
 61      this property.
 62
 63  dma-coherent: true
 64
 65  msi-parent: true
 66
 67  iommu-map: true
 68
 69  interrupts:
 70    minItems: 1
 71    maxItems: 2
 72
 73  interrupt-names:
 74    minItems: 1
 75    maxItems: 2
 76
 77  num-viewport:
 78    $ref: /schemas/types.yaml#/definitions/uint32
 79    deprecated: true
 80    description:
 81      Number of outbound view ports configured in hardware. It's the same as
 82      the number of outbound AT windows.
 83    maximum: 256
 84
 85required:
 86  - compatible
 87  - reg
 88  - reg-names
 89  - "#address-cells"
 90  - "#size-cells"
 91  - device_type
 92  - bus-range
 93  - ranges
 94  - interrupts
 95  - interrupt-names
 96  - "#interrupt-cells"
 97  - interrupt-map-mask
 98  - interrupt-map
 99
100allOf:
101  - $ref: /schemas/pci/pci-bus.yaml#
102
103  - if:
104      properties:
105        compatible:
106          enum:
107            - fsl,ls1028a-pcie
108            - fsl,ls1046a-pcie
109            - fsl,ls1043a-pcie
110            - fsl,ls1012a-pcie
111    then:
112      properties:
113        interrupts:
114          maxItems: 2
115        interrupt-names:
116          items:
117            - const: pme
118            - const: aer
119
120  - if:
121      properties:
122        compatible:
123          enum:
124            - fsl,ls2080a-pcie
125            - fsl,ls2085a-pcie
126            - fsl,ls2088a-pcie
127    then:
128      properties:
129        interrupts:
130          maxItems: 1
131        interrupt-names:
132          items:
133            - const: intr
134
135  - if:
136      properties:
137        compatible:
138          enum:
139            - fsl,ls1088a-pcie
140    then:
141      properties:
142        interrupts:
143          maxItems: 1
144        interrupt-names:
145          items:
146            - const: aer
147
148unevaluatedProperties: false
149
150examples:
151  - |
152    #include <dt-bindings/interrupt-controller/arm-gic.h>
153
154    soc {
155      #address-cells = <2>;
156      #size-cells = <2>;
157
158      pcie@3400000 {
159        compatible = "fsl,ls1088a-pcie";
160        reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
161            <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
162        reg-names = "regs", "config";
163        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
164        interrupt-names = "aer";
165        #address-cells = <3>;
166        #size-cells = <2>;
167        dma-coherent;
168        device_type = "pci";
169        bus-range = <0x0 0xff>;
170        ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
171                 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
172        msi-parent = <&its>;
173        #interrupt-cells = <1>;
174        interrupt-map-mask = <0 0 0 7>;
175        interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
176                        <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
177                        <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
178                        <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
179        iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
180      };
181    };
182...