fsl,imx6q-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX6 PCIe host controller
  8
  9maintainers:
 10  - Lucas Stach <l.stach@pengutronix.de>
 11  - Richard Zhu <hongxing.zhu@nxp.com>
 12
 13description: |+
 14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
 16  The controller instances are dual mode where in they can work either in
 17  Root Port mode or Endpoint mode but one at a time.
 18
 19  See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
 20  bindings.
 21
 22properties:
 23  compatible:
 24    enum:
 25      - fsl,imx6q-pcie
 26      - fsl,imx6sx-pcie
 27      - fsl,imx6qp-pcie
 28      - fsl,imx7d-pcie
 29      - fsl,imx8mq-pcie
 30      - fsl,imx8mm-pcie
 31      - fsl,imx8mp-pcie
 32      - fsl,imx95-pcie
 33      - fsl,imx8q-pcie
 34
 35  clocks:
 36    minItems: 3
 37    items:
 38      - description: PCIe bridge clock.
 39      - description: PCIe bus clock.
 40      - description: PCIe PHY clock.
 41      - description: Additional required clock entry for imx6sx-pcie,
 42           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
 43      - description: PCIe reference clock.
 44
 45  clock-names:
 46    minItems: 3
 47    maxItems: 5
 48
 49  interrupts:
 50    minItems: 1
 51    items:
 52      - description: builtin MSI controller.
 53      - description: builtin DMA controller.
 54
 55  interrupt-names:
 56    minItems: 1
 57    items:
 58      - const: msi
 59      - const: dma
 60
 61  reset-gpio:
 62    description: Should specify the GPIO for controlling the PCI bus device
 63      reset signal. It's not polarity aware and defaults to active-low reset
 64      sequence (L=reset state, H=operation state) (optional required).
 65
 66  reset-gpio-active-high:
 67    description: If present then the reset sequence using the GPIO
 68      specified in the "reset-gpio" property is reversed (H=reset state,
 69      L=operation state) (optional required).
 70    type: boolean
 71
 72required:
 73  - compatible
 74  - reg
 75  - reg-names
 76  - "#address-cells"
 77  - "#size-cells"
 78  - device_type
 79  - bus-range
 80  - ranges
 81  - interrupts
 82  - interrupt-names
 83  - "#interrupt-cells"
 84  - interrupt-map-mask
 85  - interrupt-map
 86
 87allOf:
 88  - $ref: /schemas/pci/snps,dw-pcie.yaml#
 89  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
 90  - if:
 91      properties:
 92        compatible:
 93          enum:
 94            - fsl,imx6q-pcie
 95            - fsl,imx6sx-pcie
 96            - fsl,imx6qp-pcie
 97            - fsl,imx7d-pcie
 98            - fsl,imx8mq-pcie
 99            - fsl,imx8mm-pcie
100            - fsl,imx8mp-pcie
101    then:
102      properties:
103        reg:
104          maxItems: 2
105        reg-names:
106          items:
107            - const: dbi
108            - const: config
109
110  - if:
111      properties:
112        compatible:
113          enum:
114            - fsl,imx95-pcie
115    then:
116      properties:
117        reg:
118          minItems: 4
119          maxItems: 4
120        reg-names:
121          items:
122            - const: dbi
123            - const: config
124            - const: atu
125            - const: app
126
127  - if:
128      properties:
129        compatible:
130          enum:
131            - fsl,imx6sx-pcie
132    then:
133      properties:
134        clocks:
135          maxItems: 4
136        clock-names:
137          items:
138            - const: pcie
139            - const: pcie_bus
140            - const: pcie_phy
141            - const: pcie_inbound_axi
142
143  - if:
144      properties:
145        compatible:
146          enum:
147            - fsl,imx8mq-pcie
148    then:
149      properties:
150        clocks:
151          maxItems: 4
152        clock-names:
153          items:
154            - const: pcie
155            - const: pcie_bus
156            - const: pcie_phy
157            - const: pcie_aux
158
159  - if:
160      properties:
161        compatible:
162          enum:
163            - fsl,imx6q-pcie
164            - fsl,imx6qp-pcie
165            - fsl,imx7d-pcie
166    then:
167      properties:
168        clocks:
169          maxItems: 3
170        clock-names:
171          items:
172            - const: pcie
173            - const: pcie_bus
174            - const: pcie_phy
175
176  - if:
177      properties:
178        compatible:
179          enum:
180            - fsl,imx8mm-pcie
181            - fsl,imx8mp-pcie
182    then:
183      properties:
184        clocks:
185          maxItems: 3
186        clock-names:
187          items:
188            - const: pcie
189            - const: pcie_bus
190            - const: pcie_aux
191
192  - if:
193      properties:
194        compatible:
195          enum:
196            - fsl,imx8q-pcie
197    then:
198      properties:
199        clocks:
200          maxItems: 3
201        clock-names:
202          items:
203            - const: dbi
204            - const: mstr
205            - const: slv
206
207  - if:
208      properties:
209        compatible:
210          enum:
211            - fsl,imx95-pcie
212    then:
213      properties:
214        clocks:
215          maxItems: 5
216        clock-names:
217          items:
218            - const: pcie
219            - const: pcie_bus
220            - const: pcie_phy
221            - const: pcie_aux
222            - const: ref
223
224unevaluatedProperties: false
225
226examples:
227  - |
228    #include <dt-bindings/clock/imx6qdl-clock.h>
229    #include <dt-bindings/interrupt-controller/arm-gic.h>
230
231    pcie: pcie@1ffc000 {
232        compatible = "fsl,imx6q-pcie";
233        reg = <0x01ffc000 0x04000>,
234              <0x01f00000 0x80000>;
235        reg-names = "dbi", "config";
236        #address-cells = <3>;
237        #size-cells = <2>;
238        device_type = "pci";
239        bus-range = <0x00 0xff>;
240        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
241                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
242        num-lanes = <1>;
243        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
244        interrupt-names = "msi";
245        #interrupt-cells = <1>;
246        interrupt-map-mask = <0 0 0 0x7>;
247        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
248                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
249                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
250                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
251        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
252                <&clks IMX6QDL_CLK_LVDS1_GATE>,
253                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
254        clock-names = "pcie", "pcie_bus", "pcie_phy";
255    };
256...