fsl,imx6q-pcie-ep.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX6 PCIe Endpoint controller
  8
  9maintainers:
 10  - Lucas Stach <l.stach@pengutronix.de>
 11  - Richard Zhu <hongxing.zhu@nxp.com>
 12
 13description: |+
 14  This PCIe controller is based on the Synopsys DesignWare PCIe IP and
 15  thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
 16  The controller instances are dual mode where in they can work either in
 17  Root Port mode or Endpoint mode but one at a time.
 18
 19properties:
 20  compatible:
 21    enum:
 22      - fsl,imx8mm-pcie-ep
 23      - fsl,imx8mq-pcie-ep
 24      - fsl,imx8mp-pcie-ep
 25      - fsl,imx8q-pcie-ep
 26      - fsl,imx95-pcie-ep
 27
 28  clocks:
 29    minItems: 3
 30    items:
 31      - description: PCIe bridge clock.
 32      - description: PCIe bus clock.
 33      - description: PCIe PHY clock.
 34      - description: Additional required clock entry for imx6sx-pcie,
 35           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
 36
 37  clock-names:
 38    minItems: 3
 39    maxItems: 4
 40
 41  interrupts:
 42    items:
 43      - description: builtin eDMA interrupter.
 44
 45  interrupt-names:
 46    items:
 47      - const: dma
 48
 49required:
 50  - compatible
 51  - reg
 52  - reg-names
 53  - interrupts
 54  - interrupt-names
 55
 56allOf:
 57  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
 58  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
 59  - if:
 60      properties:
 61        compatible:
 62          enum:
 63            - fsl,imx8mm-pcie-ep
 64            - fsl,imx8mq-pcie-ep
 65            - fsl,imx8mp-pcie-ep
 66    then:
 67      properties:
 68        reg:
 69          minItems: 4
 70          maxItems: 4
 71        reg-names:
 72          items:
 73            - const: dbi
 74            - const: addr_space
 75            - const: dbi2
 76            - const: atu
 77
 78  - if:
 79      properties:
 80        compatible:
 81          enum:
 82            - fsl,imx8q-pcie-ep
 83    then:
 84      properties:
 85        reg:
 86          maxItems: 2
 87        reg-names:
 88          items:
 89            - const: dbi
 90            - const: addr_space
 91
 92  - if:
 93      properties:
 94        compatible:
 95          enum:
 96            - fsl,imx95-pcie-ep
 97    then:
 98      properties:
 99        reg:
100          minItems: 6
101          maxItems: 6
102        reg-names:
103          items:
104            - const: dbi
105            - const: atu
106            - const: dbi2
107            - const: app
108            - const: dma
109            - const: addr_space
110
111  - if:
112      properties:
113        compatible:
114          enum:
115            - fsl,imx8mq-pcie-ep
116            - fsl,imx95-pcie-ep
117    then:
118      properties:
119        clocks:
120          minItems: 4
121          maxItems: 4
122        clock-names:
123          items:
124            - const: pcie
125            - const: pcie_bus
126            - const: pcie_phy
127            - const: pcie_aux
128
129  - if:
130      properties:
131        compatible:
132          enum:
133            - fsl,imx8mm-pcie-ep
134            - fsl,imx8mp-pcie-ep
135    then:
136      properties:
137        clocks:
138          maxItems: 3
139        clock-names:
140          items:
141            - const: pcie
142            - const: pcie_bus
143            - const: pcie_aux
144
145  - if:
146      properties:
147        compatible:
148          enum:
149            - fsl,imxq-pcie-ep
150    then:
151      properties:
152        clocks:
153          maxItems: 3
154        clock-names:
155          items:
156            - const: dbi
157            - const: mstr
158            - const: slv
159
160unevaluatedProperties: false
161
162examples:
163  - |
164    #include <dt-bindings/clock/imx8mp-clock.h>
165    #include <dt-bindings/power/imx8mp-power.h>
166    #include <dt-bindings/reset/imx8mp-reset.h>
167    #include <dt-bindings/interrupt-controller/arm-gic.h>
168
169    pcie_ep: pcie-ep@33800000 {
170      compatible = "fsl,imx8mp-pcie-ep";
171      reg = <0x33800000 0x100000>,
172            <0x18000000 0x8000000>,
173            <0x33900000 0x100000>,
174            <0x33b00000 0x100000>;
175      reg-names = "dbi", "addr_space", "dbi2", "atu";
176      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
177               <&clk IMX8MP_CLK_HSIO_AXI>,
178               <&clk IMX8MP_CLK_PCIE_ROOT>;
179      clock-names = "pcie", "pcie_bus", "pcie_aux";
180      assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
181      assigned-clock-rates = <10000000>;
182      assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
183      num-lanes = <1>;
184      interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
185      interrupt-names = "dma";
186      fsl,max-link-speed = <3>;
187      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
188      resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
189               <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
190      reset-names = "apps", "turnoff";
191      phys = <&pcie_phy>;
192      phy-names = "pcie-phy";
193      num-ib-windows = <4>;
194      num-ob-windows = <4>;
195    };