cix,sky1-pcie-host.yaml

 1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: CIX Sky1 PCIe Root Complex
 8
 9maintainers:
10  - Hans Zhang <hans.zhang@cixtech.com>
11
12description:
13  PCIe root complex controller based on the Cadence PCIe core.
14
15allOf:
16  - $ref: /schemas/pci/pci-host-bridge.yaml#
17
18properties:
19  compatible:
20    const: cix,sky1-pcie-host
21
22  reg:
23    items:
24      - description: PCIe controller registers.
25      - description: ECAM registers.
26      - description: Remote CIX System Unit strap registers.
27      - description: Remote CIX System Unit status registers.
28      - description: Region for sending messages registers.
29
30  reg-names:
31    items:
32      - const: reg
33      - const: cfg
34      - const: rcsu_strap
35      - const: rcsu_status
36      - const: msg
37
38  ranges:
39    maxItems: 3
40
41required:
42  - compatible
43  - ranges
44  - bus-range
45  - device_type
46  - interrupt-map
47  - interrupt-map-mask
48  - msi-map
49
50unevaluatedProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/interrupt-controller/arm-gic.h>
55
56    soc {
57        #address-cells = <2>;
58        #size-cells = <2>;
59
60        pcie@a010000 {
61            compatible = "cix,sky1-pcie-host";
62            reg = <0x00 0x0a010000 0x00 0x10000>,
63                  <0x00 0x2c000000 0x00 0x4000000>,
64                  <0x00 0x0a000300 0x00 0x100>,
65                  <0x00 0x0a000400 0x00 0x100>,
66                  <0x00 0x60000000 0x00 0x00100000>;
67            reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
68            ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>,
69                     <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>,
70                     <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
71            #address-cells = <3>;
72            #size-cells = <2>;
73            bus-range = <0xc0 0xff>;
74            device_type = "pci";
75            #interrupt-cells = <1>;
76            interrupt-map-mask = <0 0 0 0x7>;
77            interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
78                            <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
79                            <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
80                            <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
81            msi-map = <0xc000 &gic_its 0xc000 0x4000>;
82        };
83    };