axis,artpec6-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright 2025 Axis AB
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Axis ARTPEC-6 PCIe host controller
  9
 10maintainers:
 11  - Jesper Nilsson <jesper.nilsson@axis.com>
 12
 13description:
 14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
 15
 16select:
 17  properties:
 18    compatible:
 19      contains:
 20        enum:
 21          - axis,artpec6-pcie
 22          - axis,artpec6-pcie-ep
 23          - axis,artpec7-pcie
 24          - axis,artpec7-pcie-ep
 25  required:
 26    - compatible
 27
 28properties:
 29  compatible:
 30    items:
 31      - enum:
 32          - axis,artpec6-pcie
 33          - axis,artpec6-pcie-ep
 34          - axis,artpec7-pcie
 35          - axis,artpec7-pcie-ep
 36      - const: snps,dw-pcie
 37
 38  reg:
 39    minItems: 3
 40    maxItems: 4
 41
 42  reg-names:
 43    minItems: 3
 44    maxItems: 4
 45
 46  interrupts:
 47    maxItems: 1
 48
 49  interrupt-names:
 50    items:
 51      - const: msi
 52
 53  axis,syscon-pcie:
 54    $ref: /schemas/types.yaml#/definitions/phandle
 55    description:
 56      System controller phandle used to enable and control the Synopsys IP.
 57
 58required:
 59  - compatible
 60  - reg
 61  - reg-names
 62  - interrupts
 63  - interrupt-names
 64  - axis,syscon-pcie
 65
 66oneOf:
 67  - $ref: snps,dw-pcie.yaml#
 68    properties:
 69      reg:
 70        maxItems: 3
 71
 72      reg-names:
 73        items:
 74          - const: dbi
 75          - const: phy
 76          - const: config
 77
 78  - $ref: snps,dw-pcie-ep.yaml#
 79    properties:
 80      reg:
 81        minItems: 4
 82
 83      reg-names:
 84        items:
 85          - const: dbi
 86          - const: dbi2
 87          - const: phy
 88          - const: addr_space
 89
 90unevaluatedProperties: false
 91
 92examples:
 93  - |
 94    #include <dt-bindings/interrupt-controller/arm-gic.h>
 95
 96    pcie@f8050000 {
 97        compatible = "axis,artpec6-pcie", "snps,dw-pcie";
 98        device_type = "pci";
 99        reg = <0xf8050000 0x2000
100              0xf8040000 0x1000
101              0xc0000000 0x2000>;
102        reg-names = "dbi", "phy", "config";
103        #address-cells = <3>;
104        #size-cells = <2>;
105        ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,
106                 <0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
107        num-lanes = <2>;
108        bus-range = <0x00 0xff>;
109        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
110        interrupt-names = "msi";
111        #interrupt-cells = <1>;
112        interrupt-map-mask = <0 0 0 0x7>;
113        interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
114                        <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
115                        <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
116                        <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
117        axis,syscon-pcie = <&syscon>;
118    };