apple,pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Apple PCIe host controller
  8
  9maintainers:
 10  - Mark Kettenis <kettenis@openbsd.org>
 11
 12description: |
 13  The Apple PCIe host controller is a PCIe host controller with
 14  multiple root ports present in Apple ARM SoC platforms, including
 15  various iPhone and iPad devices and the "Apple Silicon" Macs.
 16  The controller incorporates Synopsys DesigWare PCIe logic to
 17  implements its root ports.  But the ATU found on most DesignWare
 18  PCIe host bridges is absent.
 19
 20  On systems derived from T602x, the PHY registers are in a region
 21  separate from the port registers. In that case, there is one PHY
 22  register range per port register range.
 23
 24  All root ports share a single ECAM space, but separate GPIOs are
 25  used to take the PCI devices on those ports out of reset.  Therefore
 26  the standard "reset-gpios" and "max-link-speed" properties appear on
 27  the child nodes that represent the PCI bridges that correspond to
 28  the individual root ports.
 29
 30  MSIs are handled by the PCIe controller and translated into regular
 31  interrupts.  A range of 32 MSIs is provided.  These 32 MSIs can be
 32  distributed over the root ports as the OS sees fit by programming
 33  the PCIe controller's port registers.
 34
 35properties:
 36  compatible:
 37    oneOf:
 38      - items:
 39          - enum:
 40              - apple,t8103-pcie
 41              - apple,t8112-pcie
 42              - apple,t6000-pcie
 43          - const: apple,pcie
 44      - const: apple,t6020-pcie
 45
 46  reg:
 47    minItems: 3
 48    maxItems: 10
 49
 50  reg-names:
 51    minItems: 3
 52    items:
 53      - const: config
 54      - const: rc
 55      - const: port0
 56      - const: port1
 57      - const: port2
 58      - const: port3
 59      - const: phy0
 60      - const: phy1
 61      - const: phy2
 62      - const: phy3
 63
 64  ranges:
 65    minItems: 2
 66    maxItems: 2
 67
 68  interrupts:
 69    description:
 70      Interrupt specifiers, one for each root port.
 71    minItems: 1
 72    maxItems: 4
 73
 74  msi-parent: true
 75
 76  msi-ranges:
 77    maxItems: 1
 78
 79  iommu-map: true
 80  iommu-map-mask: true
 81
 82  power-domains:
 83    maxItems: 1
 84
 85required:
 86  - compatible
 87  - reg
 88  - reg-names
 89  - bus-range
 90  - interrupts
 91  - msi-controller
 92  - msi-parent
 93  - msi-ranges
 94
 95unevaluatedProperties: false
 96
 97allOf:
 98  - $ref: /schemas/pci/pci-host-bridge.yaml#
 99  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
100  - if:
101      properties:
102        compatible:
103          contains:
104            const: apple,t8103-pcie
105    then:
106      properties:
107        reg:
108          maxItems: 5
109        interrupts:
110          maxItems: 3
111  - if:
112      properties:
113        compatible:
114          contains:
115            const: apple,t6020-pcie
116    then:
117      properties:
118        reg-names:
119          minItems: 10
120
121examples:
122  - |
123    #include <dt-bindings/interrupt-controller/apple-aic.h>
124
125    soc {
126      #address-cells = <2>;
127      #size-cells = <2>;
128
129      pcie0: pcie@690000000 {
130        compatible = "apple,t8103-pcie", "apple,pcie";
131        device_type = "pci";
132
133        reg = <0x6 0x90000000 0x0 0x1000000>,
134              <0x6 0x80000000 0x0 0x100000>,
135              <0x6 0x81000000 0x0 0x4000>,
136              <0x6 0x82000000 0x0 0x4000>,
137              <0x6 0x83000000 0x0 0x4000>;
138        reg-names = "config", "rc", "port0", "port1", "port2";
139
140        interrupt-parent = <&aic>;
141        interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
142                     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
143                     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
144
145        msi-controller;
146        msi-parent = <&pcie0>;
147        msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
148
149        iommu-map = <0x100 &dart0 1 1>,
150                    <0x200 &dart1 1 1>,
151                    <0x300 &dart2 1 1>;
152        iommu-map-mask = <0xff00>;
153
154        bus-range = <0 3>;
155        #address-cells = <3>;
156        #size-cells = <2>;
157        ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
158                 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
159
160        power-domains = <&ps_apcie_gp>;
161        pinctrl-0 = <&pcie_pins>;
162        pinctrl-names = "default";
163
164        pci@0,0 {
165          device_type = "pci";
166          reg = <0x0 0x0 0x0 0x0 0x0>;
167          reset-gpios = <&pinctrl_ap 152 0>;
168
169          #address-cells = <3>;
170          #size-cells = <2>;
171          ranges;
172        };
173
174        pci@1,0 {
175          device_type = "pci";
176          reg = <0x800 0x0 0x0 0x0 0x0>;
177          reset-gpios = <&pinctrl_ap 153 0>;
178
179          #address-cells = <3>;
180          #size-cells = <2>;
181          ranges;
182        };
183
184        pci@2,0 {
185          device_type = "pci";
186          reg = <0x1000 0x0 0x0 0x0 0x0>;
187          reset-gpios = <&pinctrl_ap 33 0>;
188
189          #address-cells = <3>;
190          #size-cells = <2>;
191          ranges;
192        };
193      };
194    };