amlogic,axg-pcie.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Amlogic Meson AXG DWC PCIe SoC controller
  8
  9maintainers:
 10  - Neil Armstrong <neil.armstrong@linaro.org>
 11
 12description:
 13  Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
 14
 15allOf:
 16  - $ref: /schemas/pci/pci-host-bridge.yaml#
 17  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
 18
 19# We need a select here so we don't match all nodes with 'snps,dw-pcie'
 20select:
 21  properties:
 22    compatible:
 23      contains:
 24        enum:
 25          - amlogic,axg-pcie
 26          - amlogic,g12a-pcie
 27  required:
 28    - compatible
 29
 30properties:
 31  compatible:
 32    items:
 33      - enum:
 34          - amlogic,axg-pcie
 35          - amlogic,g12a-pcie
 36      - const: snps,dw-pcie
 37
 38  reg:
 39    items:
 40      - description: Data Bus Interface registers
 41      - description: Meson designed configuration registers
 42      - description: PCIe configuration space
 43
 44  reg-names:
 45    items:
 46      - const: dbi
 47      - const: cfg
 48      - const: config
 49
 50  interrupts:
 51    maxItems: 1
 52
 53  clocks:
 54    items:
 55      - description: PCIe PHY clock
 56      - description: PCIe GEN 100M PLL clock
 57      - description: PCIe RC clock gate
 58
 59  clock-names:
 60    items:
 61      - const: general
 62      - const: pclk
 63      - const: port
 64
 65  phys:
 66    maxItems: 1
 67
 68  phy-names:
 69    const: pcie
 70
 71  resets:
 72    items:
 73      - description: Port Reset
 74      - description: Shared APB reset
 75
 76  reset-names:
 77    items:
 78      - const: port
 79      - const: apb
 80
 81  num-lanes:
 82    const: 1
 83
 84  power-domains:
 85    maxItems: 1
 86
 87required:
 88  - compatible
 89  - reg
 90  - reg-names
 91  - interrupts
 92  - clocks
 93  - clock-names
 94  - "#address-cells"
 95  - "#size-cells"
 96  - "#interrupt-cells"
 97  - interrupt-map
 98  - interrupt-map-mask
 99  - ranges
100  - bus-range
101  - device_type
102  - num-lanes
103  - phys
104  - phy-names
105  - resets
106  - reset-names
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    #include <dt-bindings/interrupt-controller/irq.h>
113    #include <dt-bindings/interrupt-controller/arm-gic.h>
114    pcie: pcie@f9800000 {
115        compatible = "amlogic,axg-pcie", "snps,dw-pcie";
116        reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
117        reg-names = "dbi", "cfg", "config";
118        interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
119        clocks = <&clk_phy>, <&pclk>, <&clk_port>;
120        clock-names = "general", "pclk", "port";
121        resets = <&reset_pcie_port>, <&reset_pcie_apb>;
122        reset-names = "port", "apb";
123        phys = <&pcie_phy>;
124        phy-names = "pcie";
125        #interrupt-cells = <1>;
126        interrupt-map-mask = <0 0 0 0>;
127        interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
128        bus-range = <0x0 0xff>;
129        #address-cells = <3>;
130        #size-cells = <2>;
131        device_type = "pci";
132        num-lanes = <1>;
133        ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;
134    };
135...