allwinner,sun50i-h6-operating-points.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Allwinner H6 CPU OPP
  8
  9maintainers:
 10  - Chen-Yu Tsai <wens@csie.org>
 11  - Maxime Ripard <mripard@kernel.org>
 12
 13description: |
 14  For some SoCs, the CPU frequency subset and voltage value of each
 15  OPP varies based on the silicon variant in use. Allwinner Process
 16  Voltage Scaling Tables define the voltage and frequency values based
 17  on the speedbin blown in the efuse combination.
 18
 19allOf:
 20  - $ref: opp-v2-base.yaml#
 21
 22properties:
 23  compatible:
 24    enum:
 25      - allwinner,sun50i-a100-operating-points
 26      - allwinner,sun50i-h6-operating-points
 27      - allwinner,sun50i-h616-operating-points
 28
 29  nvmem-cells:
 30    description: |
 31      A phandle pointing to a nvmem-cells node representing the efuse
 32      register that has information about the speedbin that is used
 33      to select the right frequency/voltage value pair. Please refer
 34      to the nvmem-cells bindings in
 35      Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the
 36      examples below.
 37
 38  opp-shared: true
 39
 40required:
 41  - compatible
 42  - nvmem-cells
 43
 44patternProperties:
 45  "^opp-[0-9]+$":
 46    type: object
 47
 48    properties:
 49      opp-hz: true
 50      clock-latency-ns: true
 51      opp-microvolt: true
 52      opp-supported-hw:
 53        maxItems: 1
 54        description:
 55          A single 32 bit bitmap value, representing compatible HW, one
 56          bit per speed bin index.
 57
 58    patternProperties:
 59      "^opp-microvolt-speed[0-9]$": true
 60
 61    required:
 62      - opp-hz
 63
 64    unevaluatedProperties: false
 65
 66additionalProperties: false
 67
 68examples:
 69  - |
 70    cpu_opp_table: opp-table {
 71        compatible = "allwinner,sun50i-h6-operating-points";
 72        nvmem-cells = <&speedbin_efuse>;
 73        opp-shared;
 74
 75        opp-480000000 {
 76            clock-latency-ns = <244144>; /* 8 32k periods */
 77            opp-hz = /bits/ 64 <480000000>;
 78
 79            opp-microvolt-speed0 = <880000>;
 80            opp-microvolt-speed1 = <820000>;
 81            opp-microvolt-speed2 = <800000>;
 82        };
 83
 84        opp-1080000000 {
 85            clock-latency-ns = <244144>; /* 8 32k periods */
 86            opp-hz = /bits/ 64 <1080000000>;
 87
 88            opp-microvolt-speed0 = <1060000>;
 89            opp-microvolt-speed1 = <880000>;
 90            opp-microvolt-speed2 = <840000>;
 91        };
 92
 93        opp-1488000000 {
 94            clock-latency-ns = <244144>; /* 8 32k periods */
 95            opp-hz = /bits/ 64 <1488000000>;
 96
 97            opp-microvolt-speed0 = <1160000>;
 98            opp-microvolt-speed1 = <1000000>;
 99            opp-microvolt-speed2 = <960000>;
100        };
101    };
102
103  - |
104    opp-table {
105        compatible = "allwinner,sun50i-h616-operating-points";
106        nvmem-cells = <&speedbin_efuse>;
107        opp-shared;
108
109        opp-480000000 {
110            clock-latency-ns = <244144>; /* 8 32k periods */
111            opp-hz = /bits/ 64 <480000000>;
112
113            opp-microvolt = <900000>;
114            opp-supported-hw = <0x1f>;
115        };
116
117        opp-792000000 {
118            clock-latency-ns = <244144>; /* 8 32k periods */
119            opp-hz = /bits/ 64 <792000000>;
120
121            opp-microvolt-speed1 = <900000>;
122            opp-microvolt-speed4 = <940000>;
123            opp-supported-hw = <0x12>;
124        };
125
126        opp-1512000000 {
127            clock-latency-ns = <244144>; /* 8 32k periods */
128            opp-hz = /bits/ 64 <1512000000>;
129
130            opp-microvolt = <1100000>;
131            opp-supported-hw = <0x0a>;
132        };
133    };
134
135...