rockchip,rk3588-rknn-core.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Neural Processing Unit IP from Rockchip
  8
  9maintainers:
 10  - Tomeu Vizoso <tomeu@tomeuvizoso.net>
 11
 12description:
 13  Rockchip IP for accelerating inference of neural networks.
 14
 15  There is to be a node per each NPU core in the SoC, and each core should reference all the
 16  resources that it needs to function, such as clocks, power domains, and resets.
 17
 18properties:
 19  $nodename:
 20    pattern: '^npu@[a-f0-9]+$'
 21
 22  compatible:
 23    enum:
 24      - rockchip,rk3588-rknn-core
 25
 26  reg:
 27    maxItems: 3
 28
 29  reg-names:
 30    items:
 31      - const: pc # Program Control-related registers
 32      - const: cna # Convolution Neural Network Accelerator registers
 33      - const: core # Main NPU core processing unit registers
 34
 35  clocks:
 36    maxItems: 4
 37
 38  clock-names:
 39    items:
 40      - const: aclk
 41      - const: hclk
 42      - const: npu
 43      - const: pclk
 44
 45  interrupts:
 46    maxItems: 1
 47
 48  iommus:
 49    maxItems: 1
 50
 51  npu-supply: true
 52
 53  power-domains:
 54    maxItems: 1
 55
 56  resets:
 57    maxItems: 2
 58
 59  reset-names:
 60    items:
 61      - const: srst_a
 62      - const: srst_h
 63
 64  sram-supply: true
 65
 66required:
 67  - compatible
 68  - reg
 69  - reg-names
 70  - clocks
 71  - clock-names
 72  - interrupts
 73  - iommus
 74  - power-domains
 75  - resets
 76  - reset-names
 77  - npu-supply
 78  - sram-supply
 79
 80additionalProperties: false
 81
 82examples:
 83  - |
 84    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
 85    #include <dt-bindings/interrupt-controller/irq.h>
 86    #include <dt-bindings/interrupt-controller/arm-gic.h>
 87    #include <dt-bindings/power/rk3588-power.h>
 88    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
 89
 90    bus {
 91      #address-cells = <2>;
 92      #size-cells = <2>;
 93
 94      npu@fdab0000 {
 95        compatible = "rockchip,rk3588-rknn-core";
 96        reg = <0x0 0xfdab0000 0x0 0x1000>,
 97              <0x0 0xfdab1000 0x0 0x1000>,
 98              <0x0 0xfdab3000 0x0 0x1000>;
 99        reg-names = "pc", "cna", "core";
100        clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
101                 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
102        clock-names = "aclk", "hclk", "npu", "pclk";
103        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
104        iommus = <&rknn_mmu_0>;
105        npu-supply = <&vdd_npu_s0>;
106        power-domains = <&power RK3588_PD_NPUTOP>;
107        resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
108        reset-names = "srst_a", "srst_h";
109        sram-supply = <&vdd_npu_mem_s0>;
110      };
111    };
112...