tesla,fsd-ethqos.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/tesla,fsd-ethqos.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: FSD Ethernet Quality of Service
  8
  9maintainers:
 10  - Swathi K S <swathi.ks@samsung.com>
 11
 12description:
 13  Tesla ethernet devices based on dwmmac support Gigabit ethernet.
 14
 15allOf:
 16  - $ref: snps,dwmac.yaml#
 17
 18properties:
 19  compatible:
 20    const: tesla,fsd-ethqos
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  interrupt-names:
 29    items:
 30      - const: macirq
 31
 32  clocks:
 33    minItems: 5
 34    items:
 35      - description: PTP clock
 36      - description: Master bus clock
 37      - description: Slave bus clock
 38      - description: MAC TX clock
 39      - description: MAC RX clock
 40      - description: Master2 bus clock
 41      - description: Slave2 bus clock
 42      - description: RX MUX clock
 43      - description: PHY RX clock
 44      - description: PERIC RGMII clock
 45
 46  clock-names:
 47    minItems: 5
 48    items:
 49      - const: ptp_ref
 50      - const: master_bus
 51      - const: slave_bus
 52      - const: tx
 53      - const: rx
 54      - const: master2_bus
 55      - const: slave2_bus
 56      - const: eqos_rxclk_mux
 57      - const: eqos_phyrxclk
 58      - const: dout_peric_rgmii_clk
 59
 60  iommus:
 61    maxItems: 1
 62
 63  phy-mode:
 64    enum:
 65      - rgmii
 66      - rgmii-id
 67      - rgmii-rxid
 68      - rgmii-txid
 69
 70required:
 71  - compatible
 72  - reg
 73  - interrupts
 74  - clocks
 75  - clock-names
 76  - iommus
 77  - phy-mode
 78
 79unevaluatedProperties: false
 80
 81examples:
 82  - |
 83    #include <dt-bindings/clock/fsd-clk.h>
 84    #include <dt-bindings/interrupt-controller/arm-gic.h>
 85    soc {
 86        #address-cells = <2>;
 87        #size-cells = <2>;
 88        ethernet1: ethernet@14300000 {
 89            compatible = "tesla,fsd-ethqos";
 90            reg = <0x0 0x14300000 0x0 0x10000>;
 91            interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 92            interrupt-names = "macirq";
 93            clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
 94                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
 95                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
 96                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
 97                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
 98                     <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
 99                     <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
100                     <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
101                     <&clock_peric PERIC_EQOS_PHYRXCLK>,
102                     <&clock_peric PERIC_DOUT_RGMII_CLK>;
103            clock-names = "ptp_ref", "master_bus", "slave_bus","tx",
104                          "rx", "master2_bus", "slave2_bus", "eqos_rxclk_mux",
105                          "eqos_phyrxclk","dout_peric_rgmii_clk";
106            assigned-clocks = <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
107                              <&clock_peric PERIC_EQOS_PHYRXCLK>;
108            assigned-clock-parents = <&clock_peric PERIC_EQOS_PHYRXCLK>;
109            pinctrl-names = "default";
110            pinctrl-0 = <&eth1_tx_clk>, <&eth1_tx_data>, <&eth1_tx_ctrl>,
111                        <&eth1_phy_intr>, <&eth1_rx_clk>, <&eth1_rx_data>,
112                        <&eth1_rx_ctrl>, <&eth1_mdio>;
113            iommus = <&smmu_peric 0x0 0x1>;
114            phy-mode = "rgmii-id";
115        };
116    };
117
118...