renesas,rzv2h-gbeth.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)
  8
  9maintainers:
 10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 11
 12select:
 13  properties:
 14    compatible:
 15      contains:
 16        enum:
 17          - renesas,r9a09g047-gbeth
 18          - renesas,r9a09g056-gbeth
 19          - renesas,r9a09g057-gbeth
 20          - renesas,r9a09g077-gbeth
 21          - renesas,r9a09g087-gbeth
 22          - renesas,rzv2h-gbeth
 23  required:
 24    - compatible
 25
 26properties:
 27  compatible:
 28    oneOf:
 29      - items:
 30          - enum:
 31              - renesas,r9a09g047-gbeth # RZ/G3E
 32              - renesas,r9a09g056-gbeth # RZ/V2N
 33              - renesas,r9a09g057-gbeth # RZ/V2H(P)
 34          - const: renesas,rzv2h-gbeth
 35          - const: snps,dwmac-5.20
 36      - items:
 37          - const: renesas,r9a09g077-gbeth # RZ/T2H
 38          - const: snps,dwmac-5.20
 39      - items:
 40          - const: renesas,r9a09g087-gbeth # RZ/N2H
 41          - const: renesas,r9a09g077-gbeth
 42          - const: snps,dwmac-5.20
 43
 44  reg:
 45    maxItems: 1
 46
 47  clocks:
 48    oneOf:
 49      - items:
 50          - description: CSR clock
 51          - description: AXI system clock
 52          - description: PTP clock
 53          - description: TX clock
 54          - description: RX clock
 55          - description: TX clock phase-shifted by 180 degrees
 56          - description: RX clock phase-shifted by 180 degrees
 57      - items:
 58          - description: CSR clock
 59          - description: AXI system clock
 60          - description: TX clock
 61
 62  clock-names:
 63    oneOf:
 64      - items:
 65          - const: stmmaceth
 66          - const: pclk
 67          - const: ptp_ref
 68          - const: tx
 69          - const: rx
 70          - const: tx-180
 71          - const: rx-180
 72      - items:
 73          - const: stmmaceth
 74          - const: pclk
 75          - const: tx
 76
 77  interrupt-names:
 78    oneOf:
 79      - items:
 80          - const: macirq
 81          - const: eth_wake_irq
 82          - const: eth_lpi
 83          - const: rx-queue-0
 84          - const: rx-queue-1
 85          - const: rx-queue-2
 86          - const: rx-queue-3
 87          - const: tx-queue-0
 88          - const: tx-queue-1
 89          - const: tx-queue-2
 90          - const: tx-queue-3
 91      - items:
 92          - const: macirq
 93          - const: eth_wake_irq
 94          - const: eth_lpi
 95          - const: rx-queue-0
 96          - const: rx-queue-1
 97          - const: rx-queue-2
 98          - const: rx-queue-3
 99          - const: rx-queue-4
100          - const: rx-queue-5
101          - const: rx-queue-6
102          - const: rx-queue-7
103          - const: tx-queue-0
104          - const: tx-queue-1
105          - const: tx-queue-2
106          - const: tx-queue-3
107          - const: tx-queue-4
108          - const: tx-queue-5
109          - const: tx-queue-6
110          - const: tx-queue-7
111
112  resets:
113    oneOf:
114      - items:
115          - description: AXI power-on system reset
116      - items:
117          - description: AXI power-on system reset
118          - description: AHB reset
119
120  pcs-handle:
121    description:
122      phandle pointing to a PCS sub-node compatible with
123      Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml#
124      (Refer RZ/T2H portion in the DT-binding file)
125
126required:
127  - compatible
128  - reg
129  - clocks
130  - clock-names
131  - interrupts
132  - interrupt-names
133  - resets
134
135allOf:
136  - $ref: snps,dwmac.yaml#
137
138  - if:
139      properties:
140        compatible:
141          contains:
142            const: renesas,r9a09g077-gbeth
143    then:
144      properties:
145        clocks:
146          maxItems: 3
147
148        clock-names:
149          maxItems: 3
150
151        interrupts:
152          minItems: 19
153
154        interrupt-names:
155          minItems: 19
156
157        resets:
158          minItems: 2
159
160        reset-names:
161          minItems: 2
162
163      required:
164        - reset-names
165    else:
166      properties:
167        clocks:
168          minItems: 7
169
170        clock-names:
171          minItems: 7
172
173        interrupts:
174          minItems: 11
175          maxItems: 11
176
177        interrupt-names:
178          minItems: 11
179          maxItems: 11
180
181        resets:
182          maxItems: 1
183
184        pcs-handle: false
185
186        reset-names: false
187
188unevaluatedProperties: false
189
190examples:
191  - |
192    #include <dt-bindings/clock/renesas-cpg-mssr.h>
193    #include <dt-bindings/interrupt-controller/arm-gic.h>
194
195    ethernet@15c30000 {
196        compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
197        reg = <0x15c30000 0x10000>;
198        clocks =  <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
199                  <&ptp_clock>, <&cpg CPG_MOD 0xb8>,
200                  <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>,
201                  <&cpg CPG_MOD 0xbb>;
202        clock-names = "stmmaceth", "pclk", "ptp_ref",
203                      "tx", "rx", "tx-180", "rx-180";
204        resets = <&cpg 0xb0>;
205        interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
206                     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
207                     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
208                     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
209                     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
210                     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
211                     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
212                     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
213                     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
214                     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
215                     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
216        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
217                          "rx-queue-0", "rx-queue-1", "rx-queue-2",
218                          "rx-queue-3", "tx-queue-0", "tx-queue-1",
219                          "tx-queue-2", "tx-queue-3";
220        phy-mode = "rgmii-id";
221        snps,multicast-filter-bins = <256>;
222        snps,perfect-filter-entries = <128>;
223        rx-fifo-depth = <8192>;
224        tx-fifo-depth = <8192>;
225        snps,fixed-burst;
226        snps,force_thresh_dma_mode;
227        snps,axi-config = <&stmmac_axi_setup>;
228        snps,mtl-rx-config = <&mtl_rx_setup>;
229        snps,mtl-tx-config = <&mtl_tx_setup>;
230        snps,txpbl = <32>;
231        snps,rxpbl = <32>;
232        phy-handle = <&phy0>;
233
234        stmmac_axi_setup: stmmac-axi-config {
235            snps,lpi_en;
236            snps,wr_osr_lmt = <0xf>;
237            snps,rd_osr_lmt = <0xf>;
238            snps,blen = <16 8 4 0 0 0 0>;
239        };
240
241        mtl_rx_setup: rx-queues-config {
242            snps,rx-queues-to-use = <4>;
243            snps,rx-sched-sp;
244
245            queue0 {
246                snps,dcb-algorithm;
247                snps,priority = <0x1>;
248                snps,map-to-dma-channel = <0>;
249            };
250
251            queue1 {
252                snps,dcb-algorithm;
253                snps,priority = <0x2>;
254                snps,map-to-dma-channel = <1>;
255            };
256
257            queue2 {
258                snps,dcb-algorithm;
259                snps,priority = <0x4>;
260                snps,map-to-dma-channel = <2>;
261            };
262
263            queue3 {
264                snps,dcb-algorithm;
265                snps,priority = <0x8>;
266                snps,map-to-dma-channel = <3>;
267            };
268        };
269
270        mtl_tx_setup: tx-queues-config {
271            snps,tx-queues-to-use = <4>;
272
273            queue0 {
274                snps,dcb-algorithm;
275                snps,priority = <0x1>;
276            };
277
278            queue1 {
279                snps,dcb-algorithm;
280                snps,priority = <0x2>;
281            };
282
283            queue2 {
284                snps,dcb-algorithm;
285                snps,priority = <0x4>;
286            };
287
288            queue3 {
289                snps,dcb-algorithm;
290                snps,priority = <0x1>;
291            };
292        };
293
294        mdio {
295            #address-cells = <1>;
296            #size-cells = <0>;
297            compatible = "snps,dwmac-mdio";
298
299            phy0: ethernet-phy@0 {
300                reg = <0>;
301            };
302        };
303    };