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renesas,r8a779f0-ether-switch.yaml
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linux-6.19.14/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/renesas,r8a779f0-ether-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas Ethernet Switch 8 9maintainers: 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11 12properties: 13 compatible: 14 const: renesas,r8a779f0-ether-switch 15 16 reg: 17 maxItems: 2 18 19 reg-names: 20 items: 21 - const: base 22 - const: secure_base 23 24 interrupts: 25 maxItems: 47 26 27 interrupt-names: 28 items: 29 - const: mfwd_error 30 - const: race_error 31 - const: coma_error 32 - const: gwca0_error 33 - const: gwca1_error 34 - const: etha0_error 35 - const: etha1_error 36 - const: etha2_error 37 - const: gptp0_status 38 - const: gptp1_status 39 - const: mfwd_status 40 - const: race_status 41 - const: coma_status 42 - const: gwca0_status 43 - const: gwca1_status 44 - const: etha0_status 45 - const: etha1_status 46 - const: etha2_status 47 - const: rmac0_status 48 - const: rmac1_status 49 - const: rmac2_status 50 - const: gwca0_rxtx0 51 - const: gwca0_rxtx1 52 - const: gwca0_rxtx2 53 - const: gwca0_rxtx3 54 - const: gwca0_rxtx4 55 - const: gwca0_rxtx5 56 - const: gwca0_rxtx6 57 - const: gwca0_rxtx7 58 - const: gwca1_rxtx0 59 - const: gwca1_rxtx1 60 - const: gwca1_rxtx2 61 - const: gwca1_rxtx3 62 - const: gwca1_rxtx4 63 - const: gwca1_rxtx5 64 - const: gwca1_rxtx6 65 - const: gwca1_rxtx7 66 - const: gwca0_rxts0 67 - const: gwca0_rxts1 68 - const: gwca1_rxts0 69 - const: gwca1_rxts1 70 - const: rmac0_mdio 71 - const: rmac1_mdio 72 - const: rmac2_mdio 73 - const: rmac0_phy 74 - const: rmac1_phy 75 - const: rmac2_phy 76 77 clocks: 78 maxItems: 1 79 80 resets: 81 maxItems: 1 82 83 iommus: 84 maxItems: 16 85 86 power-domains: 87 maxItems: 1 88 89 ethernet-ports: 90 type: object 91 additionalProperties: false 92 93 properties: 94 '#address-cells': 95 description: Port number of ETHA (TSNA). 96 const: 1 97 98 '#size-cells': 99 const: 0 100 101 patternProperties: 102 "^port@[0-9a-f]+$": 103 type: object 104 $ref: /schemas/net/ethernet-controller.yaml# 105 unevaluatedProperties: false 106 107 properties: 108 reg: 109 maxItems: 1 110 description: 111 Port number of ETHA (TSNA). 112 113 phys: 114 maxItems: 1 115 description: 116 Phandle of an Ethernet SERDES. 117 118 mdio: 119 $ref: /schemas/net/mdio.yaml# 120 unevaluatedProperties: false 121 122 required: 123 - reg 124 - phy-handle 125 - phy-mode 126 - phys 127 - mdio 128 129required: 130 - compatible 131 - reg 132 - reg-names 133 - interrupts 134 - interrupt-names 135 - clocks 136 - resets 137 - power-domains 138 - ethernet-ports 139 140additionalProperties: false 141 142examples: 143 - | 144 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 145 #include <dt-bindings/interrupt-controller/arm-gic.h> 146 #include <dt-bindings/power/r8a779f0-sysc.h> 147 148 ethernet@e6880000 { 149 compatible = "renesas,r8a779f0-ether-switch"; 150 reg = <0xe6880000 0x20000>, <0xe68c0000 0x20000>; 151 reg-names = "base", "secure_base"; 152 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-names = "mfwd_error", "race_error", 200 "coma_error", "gwca0_error", 201 "gwca1_error", "etha0_error", 202 "etha1_error", "etha2_error", 203 "gptp0_status", "gptp1_status", 204 "mfwd_status", "race_status", 205 "coma_status", "gwca0_status", 206 "gwca1_status", "etha0_status", 207 "etha1_status", "etha2_status", 208 "rmac0_status", "rmac1_status", 209 "rmac2_status", 210 "gwca0_rxtx0", "gwca0_rxtx1", 211 "gwca0_rxtx2", "gwca0_rxtx3", 212 "gwca0_rxtx4", "gwca0_rxtx5", 213 "gwca0_rxtx6", "gwca0_rxtx7", 214 "gwca1_rxtx0", "gwca1_rxtx1", 215 "gwca1_rxtx2", "gwca1_rxtx3", 216 "gwca1_rxtx4", "gwca1_rxtx5", 217 "gwca1_rxtx6", "gwca1_rxtx7", 218 "gwca0_rxts0", "gwca0_rxts1", 219 "gwca1_rxts0", "gwca1_rxts1", 220 "rmac0_mdio", "rmac1_mdio", 221 "rmac2_mdio", 222 "rmac0_phy", "rmac1_phy", 223 "rmac2_phy"; 224 clocks = <&cpg CPG_MOD 1505>; 225 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 226 resets = <&cpg 1505>; 227 228 ethernet-ports { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 port@0 { 232 reg = <0>; 233 phy-handle = <ð_phy0>; 234 phy-mode = "sgmii"; 235 phys = <ð_serdes 0>; 236 mdio { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 }; 240 }; 241 port@1 { 242 reg = <1>; 243 phy-handle = <ð_phy1>; 244 phy-mode = "sgmii"; 245 phys = <ð_serdes 1>; 246 mdio { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 }; 250 }; 251 port@2 { 252 reg = <2>; 253 phy-handle = <ð_phy2>; 254 phy-mode = "sgmii"; 255 phys = <ð_serdes 2>; 256 mdio { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 }; 260 }; 261 }; 262 };
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