renesas,ether.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/renesas,ether.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas Electronics SH EtherMAC
  8
  9allOf:
 10  - $ref: ethernet-controller.yaml#
 11
 12maintainers:
 13  - Sergei Shtylyov <sergei.shtylyov@gmail.com>
 14
 15properties:
 16  compatible:
 17    oneOf:
 18      - items:
 19          - enum:
 20              - renesas,gether-r8a7740   # device is a part of R8A7740 SoC
 21              - renesas,gether-r8a77980  # device is a part of R8A77980 SoC
 22              - renesas,ether-r7s72100   # device is a part of R7S72100 SoC
 23              - renesas,ether-r7s9210    # device is a part of R7S9210 SoC
 24      - items:
 25          - enum:
 26              - renesas,ether-r8a7778    # device is a part of R8A7778 SoC
 27              - renesas,ether-r8a7779    # device is a part of R8A7779 SoC
 28          - enum:
 29              - renesas,rcar-gen1-ether  # a generic R-Car Gen1 device
 30      - items:
 31          - enum:
 32              - renesas,ether-r8a7742    # device is a part of R8A7742 SoC
 33              - renesas,ether-r8a7743    # device is a part of R8A7743 SoC
 34              - renesas,ether-r8a7745    # device is a part of R8A7745 SoC
 35              - renesas,ether-r8a7790    # device is a part of R8A7790 SoC
 36              - renesas,ether-r8a7791    # device is a part of R8A7791 SoC
 37              - renesas,ether-r8a7793    # device is a part of R8A7793 SoC
 38              - renesas,ether-r8a7794    # device is a part of R8A7794 SoC
 39          - enum:
 40              - renesas,rcar-gen2-ether  # a generic R-Car Gen2 or RZ/G1 device
 41
 42  reg:
 43    items:
 44      - description: E-DMAC/feLic registers
 45      - description: TSU registers
 46    minItems: 1
 47
 48  interrupts:
 49    maxItems: 1
 50
 51  '#address-cells':
 52    description: number of address cells for the MDIO bus
 53    const: 1
 54
 55  '#size-cells':
 56    description: number of size cells on the MDIO bus
 57    const: 0
 58
 59  clocks:
 60    maxItems: 1
 61
 62  iommus:
 63    maxItems: 1
 64
 65  power-domains:
 66    maxItems: 1
 67
 68  resets:
 69    maxItems: 1
 70
 71  phy-mode: true
 72
 73  phy-handle: true
 74
 75  renesas,no-ether-link:
 76    type: boolean
 77    description:
 78      specify when a board does not provide a proper Ether LINK signal
 79
 80  renesas,ether-link-active-low:
 81    type: boolean
 82    description:
 83      specify when the Ether LINK signal is active-low instead of normal
 84      active-high
 85
 86patternProperties:
 87  "@[0-9a-f]$":
 88    type: object
 89
 90required:
 91  - compatible
 92  - reg
 93  - interrupts
 94  - phy-mode
 95  - phy-handle
 96  - '#address-cells'
 97  - '#size-cells'
 98  - clocks
 99
100additionalProperties: false
101
102examples:
103  # Lager board
104  - |
105    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
106    #include <dt-bindings/interrupt-controller/arm-gic.h>
107    #include <dt-bindings/power/r8a7790-sysc.h>
108    #include <dt-bindings/gpio/gpio.h>
109
110    ethernet@ee700000 {
111        compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
112        reg = <0xee700000 0x400>;
113        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
114        clocks = <&cpg CPG_MOD 813>;
115        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
116        resets = <&cpg 813>;
117        phy-mode = "rmii";
118        phy-handle = <&phy1>;
119        renesas,ether-link-active-low;
120        #address-cells = <1>;
121        #size-cells = <0>;
122
123        phy1: ethernet-phy@1 {
124            compatible = "ethernet-phy-id0022.1537",
125                         "ethernet-phy-ieee802.3-c22";
126            reg = <1>;
127            interrupt-parent = <&irqc0>;
128            interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
129            reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
130        };
131    };