qcom,ethqos.yaml

  1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Ethernet ETHQOS device
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Konrad Dybcio <konradybcio@kernel.org>
 12
 13description:
 14  dwmmac based Qualcomm ethernet devices which support Gigabit
 15  ethernet (version v2.3.0 and onwards).
 16
 17allOf:
 18  - $ref: snps,dwmac.yaml#
 19
 20properties:
 21  compatible:
 22    oneOf:
 23      - items:
 24          - enum:
 25              - qcom,qcs615-ethqos
 26          - const: qcom,qcs404-ethqos
 27      - items:
 28          - enum:
 29              - qcom,qcs8300-ethqos
 30          - const: qcom,sa8775p-ethqos
 31      - enum:
 32          - qcom,qcs404-ethqos
 33          - qcom,sa8775p-ethqos
 34          - qcom,sc8280xp-ethqos
 35          - qcom,sm8150-ethqos
 36
 37  reg:
 38    maxItems: 2
 39
 40  reg-names:
 41    items:
 42      - const: stmmaceth
 43      - const: rgmii
 44
 45  interrupts:
 46    minItems: 1
 47    items:
 48      - description: Combined signal for various interrupt events
 49      - description: The interrupt that occurs when Rx exits the LPI state
 50      - description: The interrupt that occurs when HW safety error triggered
 51
 52  interrupt-names:
 53    minItems: 1
 54    items:
 55      - const: macirq
 56      - enum: [eth_lpi, sfty]
 57      - const: sfty
 58
 59  clocks:
 60    maxItems: 4
 61
 62  clock-names:
 63    items:
 64      - const: stmmaceth
 65      - const: pclk
 66      - const: ptp_ref
 67      - enum:
 68          - rgmii
 69          - phyaux
 70
 71  iommus:
 72    maxItems: 1
 73
 74  dma-coherent: true
 75
 76  interconnects:
 77    maxItems: 2
 78
 79  interconnect-names:
 80    items:
 81      - const: cpu-mac
 82      - const: mac-mem
 83
 84  phys: true
 85
 86  phy-names:
 87    const: serdes
 88
 89required:
 90  - compatible
 91  - clocks
 92  - clock-names
 93  - reg-names
 94
 95unevaluatedProperties: false
 96
 97examples:
 98  - |
 99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
101    #include <dt-bindings/gpio/gpio.h>
102
103    ethernet: ethernet@7a80000 {
104      compatible = "qcom,qcs404-ethqos";
105      reg = <0x07a80000 0x10000>,
106            <0x07a96000 0x100>;
107      reg-names = "stmmaceth", "rgmii";
108      clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
109      clocks = <&gcc GCC_ETH_AXI_CLK>,
110               <&gcc GCC_ETH_SLAVE_AHB_CLK>,
111               <&gcc GCC_ETH_PTP_CLK>,
112               <&gcc GCC_ETH_RGMII_CLK>;
113      interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
114                   <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
115                   <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
116      interrupt-names = "macirq", "eth_lpi", "sfty";
117
118      rx-fifo-depth = <4096>;
119      tx-fifo-depth = <4096>;
120
121      snps,tso;
122      snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
123      snps,reset-active-low;
124      snps,reset-delays-us = <0 10000 10000>;
125
126      pinctrl-names = "default";
127      pinctrl-0 = <&ethernet_defaults>;
128
129      phy-handle = <&phy1>;
130      phy-mode = "rgmii";
131      mdio {
132        #address-cells = <0x1>;
133        #size-cells = <0x0>;
134
135        compatible = "snps,dwmac-mdio";
136        phy1: phy@4 {
137          compatible = "ethernet-phy-ieee802.3-c22";
138          device_type = "ethernet-phy";
139          reg = <0x4>;
140
141          #phy-cells = <0>;
142        };
143      };
144    };