motorcomm,yt8xxx.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MotorComm yt8xxx Ethernet PHY
  8
  9maintainers:
 10  - Frank Sae <frank.sae@motor-comm.com>
 11
 12allOf:
 13  - $ref: ethernet-phy.yaml#
 14
 15properties:
 16  compatible:
 17    enum:
 18      - ethernet-phy-id4f51.e91a
 19      - ethernet-phy-id4f51.e91b
 20
 21  rx-internal-delay-ps:
 22    description: |
 23      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
 24      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
 25    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
 26            1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
 27            2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
 28    default: 1950
 29
 30  tx-internal-delay-ps:
 31    description: |
 32      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
 33      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
 34    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
 35            1950, 2100, 2250 ]
 36    default: 1950
 37
 38  motorcomm,clk-out-frequency-hz:
 39    description: clock output on clock output pin.
 40    enum: [0, 25000000, 125000000]
 41    default: 0
 42
 43  motorcomm,keep-pll-enabled:
 44    description: |
 45      If set, keep the PLL enabled even if there is no link. Useful if you
 46      want to use the clock output without an ethernet link.
 47    type: boolean
 48
 49  motorcomm,auto-sleep-disabled:
 50    description: |
 51      If set, PHY will not enter sleep mode and close AFE after unplug cable
 52      for a timer.
 53    type: boolean
 54
 55  motorcomm,rx-clk-drv-microamp:
 56    description: |
 57      drive strength of rx_clk rgmii pad.
 58      The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
 59      be configured with hardware pull-up resistors to match the SOC voltage
 60      (usually 1.8V).
 61      The software can read the registers to obtain the LDO voltage and configure
 62      the legal drive strength(curren).
 63      =====================================================
 64      | voltage |        current Available (uA)           |
 65      |   1.8v  | 1200 2100 2700 2910 3110 3600 3970 4350 |
 66      |   3.3v  | 3070 4080 4370 4680 5020 5450 5740 6140 |
 67      =====================================================
 68    enum: [ 1200, 2100, 2700, 2910, 3070, 3110, 3600, 3970,
 69            4080, 4350, 4370, 4680, 5020, 5450, 5740, 6140 ]
 70    default: 2910
 71
 72  motorcomm,rx-data-drv-microamp:
 73    description: |
 74      drive strength of rx_data/rx_ctl rgmii pad.
 75      The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
 76      be configured with hardware pull-up resistors to match the SOC voltage
 77      (usually 1.8V).
 78      The software can read the registers to obtain the LDO voltage and configure
 79      the legal drive strength(curren).
 80      =====================================================
 81      | voltage |        current Available (uA)           |
 82      |   1.8v  | 1200 2100 2700 2910 3110 3600 3970 4350 |
 83      |   3.3v  | 3070 4080 4370 4680 5020 5450 5740 6140 |
 84      =====================================================
 85    enum: [ 1200, 2100, 2700, 2910, 3070, 3110, 3600, 3970,
 86            4080, 4350, 4370, 4680, 5020, 5450, 5740, 6140 ]
 87    default: 2910
 88
 89  motorcomm,tx-clk-adj-enabled:
 90    description: |
 91      This configuration is mainly to adapt to VF2 with JH7110 SoC.
 92      Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
 93    type: boolean
 94
 95  motorcomm,tx-clk-10-inverted:
 96    description: |
 97      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
 98      Transmit PHY Clock delay train configuration when speed is 10Mbps.
 99    type: boolean
100
101  motorcomm,tx-clk-100-inverted:
102    description: |
103      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
104      Transmit PHY Clock delay train configuration when speed is 100Mbps.
105    type: boolean
106
107  motorcomm,tx-clk-1000-inverted:
108    description: |
109      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
110      Transmit PHY Clock delay train configuration when speed is 1000Mbps.
111    type: boolean
112
113unevaluatedProperties: false
114
115examples:
116  - |
117    mdio {
118        #address-cells = <1>;
119        #size-cells = <0>;
120        phy-mode = "rgmii-id";
121        ethernet-phy@4 {
122            /*  Only needed to make DT lint tools work. Do not copy/paste
123             *  into real DTS files.
124             */
125            compatible = "ethernet-phy-id4f51.e91a";
126
127            reg = <4>;
128            rx-internal-delay-ps = <2100>;
129            tx-internal-delay-ps = <150>;
130            motorcomm,clk-out-frequency-hz = <0>;
131            motorcomm,keep-pll-enabled;
132            motorcomm,auto-sleep-disabled;
133        };
134    };
135  - |
136    mdio {
137        #address-cells = <1>;
138        #size-cells = <0>;
139        phy-mode = "rgmii";
140        ethernet-phy@5 {
141            /*  Only needed to make DT lint tools work. Do not copy/paste
142             *  into real DTS files.
143             */
144            compatible = "ethernet-phy-id4f51.e91a";
145
146            reg = <5>;
147            motorcomm,clk-out-frequency-hz = <125000000>;
148            motorcomm,keep-pll-enabled;
149            motorcomm,auto-sleep-disabled;
150        };
151    };