microchip,sparx5-switch.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Microchip Sparx5 Ethernet switch controller
  8
  9maintainers:
 10  - Steen Hegelund <steen.hegelund@microchip.com>
 11  - Lars Povlsen <lars.povlsen@microchip.com>
 12  - Daniel Machon <daniel.machon@microchip.com>
 13
 14description: |
 15  The SparX-5 Enterprise Ethernet switch family provides a rich set of
 16  Enterprise switching features such as advanced TCAM-based VLAN and
 17  QoS processing enabling delivery of differentiated services, and
 18  security through TCAM-based frame processing using versatile content
 19  aware processor (VCAP).
 20
 21  IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
 22  with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
 23  IPv6 (S,G) multicast groups.
 24
 25  L3 security features include source guard and reverse path
 26  forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
 27  IP tunnels (IP over GRE/IP).
 28
 29  The SparX-5 switch family targets managed Layer 2 and Layer 3
 30  equipment in SMB, SME, and Enterprise where high port count
 31  1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
 32
 33properties:
 34  $nodename:
 35    pattern: "^switch@[0-9a-f]+$"
 36
 37  compatible:
 38    oneOf:
 39      - enum:
 40          - microchip,lan9691-switch
 41          - microchip,sparx5-switch
 42      - items:
 43          - enum:
 44              - microchip,lan969c-switch
 45              - microchip,lan969b-switch
 46              - microchip,lan969a-switch
 47              - microchip,lan9699-switch
 48              - microchip,lan9698-switch
 49              - microchip,lan9697-switch
 50              - microchip,lan9696-switch
 51              - microchip,lan9695-switch
 52              - microchip,lan9694-switch
 53              - microchip,lan9693-switch
 54              - microchip,lan9692-switch
 55          - const: microchip,lan9691-switch
 56
 57  reg:
 58    minItems: 2
 59    items:
 60      - description: cpu target
 61      - description: devices target
 62      - description: general control block target
 63
 64  reg-names:
 65    minItems: 2
 66    items:
 67      - const: cpu
 68      - const: devices
 69      - const: gcb
 70
 71  interrupts:
 72    minItems: 1
 73    items:
 74      - description: register based extraction
 75      - description: frame dma based extraction
 76      - description: ptp interrupt
 77
 78  interrupt-names:
 79    minItems: 1
 80    items:
 81      - const: xtr
 82      - const: fdma
 83      - const: ptp
 84
 85  resets:
 86    items:
 87      - description: Reset controller used for switch core reset (soft reset)
 88
 89  reset-names:
 90    items:
 91      - const: switch
 92
 93  mac-address: true
 94
 95  ethernet-ports:
 96    type: object
 97    additionalProperties: false
 98
 99    properties:
100      '#address-cells':
101        const: 1
102      '#size-cells':
103        const: 0
104
105    patternProperties:
106      "^port@[0-9a-f]+$":
107        $ref: /schemas/net/ethernet-controller.yaml#
108        unevaluatedProperties: false
109
110        properties:
111          reg:
112            description: Switch port number
113
114          phys:
115            maxItems: 1
116            description:
117              phandle of a Ethernet SerDes PHY.  This defines which SerDes
118              instance will handle the Ethernet traffic.
119
120          microchip,bandwidth:
121            description: Specifies bandwidth in Mbit/s allocated to the port.
122            $ref: /schemas/types.yaml#/definitions/uint32
123            maximum: 25000
124
125          microchip,sd-sgpio:
126            description:
127              Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
128              This is optional, and only needed if the default used index is
129              is not correct.
130            $ref: /schemas/types.yaml#/definitions/uint32
131            minimum: 0
132            maximum: 383
133
134          rx-internal-delay-ps:
135            description:
136              RGMII Receive Clock Delay defined in pico seconds, used to select
137              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
138              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
139              any delay. The Default is no delay.
140            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
141            default: 0
142
143          tx-internal-delay-ps:
144            description:
145              RGMII Transmit Clock Delay defined in pico seconds, used to select
146              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
147              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
148              any delay. The Default is no delay.
149            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
150            default: 0
151
152        required:
153          - reg
154          - phys
155          - phy-mode
156          - microchip,bandwidth
157
158        oneOf:
159          - required:
160              - phy-handle
161          - required:
162              - sfp
163              - managed
164
165required:
166  - compatible
167  - reg
168  - reg-names
169  - interrupts
170  - interrupt-names
171  - ethernet-ports
172
173allOf:
174  - if:
175      properties:
176        compatible:
177          contains:
178            enum:
179              - microchip,lan9691-switch
180    then:
181      properties:
182        reg:
183          maxItems: 2
184        reg-names:
185          maxItems: 2
186    else:
187      properties:
188        reg:
189          minItems: 3
190        reg-names:
191          minItems: 3
192
193additionalProperties: false
194
195examples:
196  - |
197    #include <dt-bindings/interrupt-controller/arm-gic.h>
198    switch: switch@600000000 {
199      compatible = "microchip,sparx5-switch";
200      reg =  <0 0x401000>,
201             <0x10004000 0x7fc000>,
202             <0x11010000 0xaf0000>;
203      reg-names = "cpu", "devices", "gcb";
204      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
205      interrupt-names = "xtr";
206      resets = <&reset 0>;
207      reset-names = "switch";
208      ethernet-ports {
209        #address-cells = <1>;
210        #size-cells = <0>;
211
212        port0: port@0 {
213          reg = <0>;
214          microchip,bandwidth = <1000>;
215          phys = <&serdes 13>;
216          phy-handle = <&phy0>;
217          phy-mode = "qsgmii";
218        };
219        /* ... */
220        /* Then the 25G interfaces */
221        port60: port@60 {
222          reg = <60>;
223          microchip,bandwidth = <25000>;
224          phys = <&serdes 29>;
225          phy-mode = "10gbase-r";
226          sfp = <&sfp_eth60>;
227          managed = "in-band-status";
228          microchip,sd-sgpio = <365>;
229        };
230        port61: port@61 {
231          reg = <61>;
232          microchip,bandwidth = <25000>;
233          phys = <&serdes 30>;
234          phy-mode = "10gbase-r";
235          sfp = <&sfp_eth61>;
236          managed = "in-band-status";
237          microchip,sd-sgpio = <369>;
238        };
239        port62: port@62 {
240          reg = <62>;
241          microchip,bandwidth = <25000>;
242          phys = <&serdes 31>;
243          phy-mode = "10gbase-r";
244          sfp = <&sfp_eth62>;
245          managed = "in-band-status";
246          microchip,sd-sgpio = <373>;
247        };
248        port63: port@63 {
249          reg = <63>;
250          microchip,bandwidth = <25000>;
251          phys = <&serdes 32>;
252          phy-mode = "10gbase-r";
253          sfp = <&sfp_eth63>;
254          managed = "in-band-status";
255          microchip,sd-sgpio = <377>;
256        };
257        /* Finally the Management interface */
258        port64: port@64 {
259          reg = <64>;
260          microchip,bandwidth = <1000>;
261          phys = <&serdes 0>;
262          phy-handle = <&phy64>;
263          phy-mode = "sgmii";
264          mac-address = [ 00 00 00 01 02 03 ];
265        };
266      };
267    };
268
269...